Phase detector and phase locked loop circuit

Details Phase detector and phase locked loop circuit Phase detector and phase locked loop circuit

2005-08-23

2005-08-23

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S023000, C327S141000, C327S157000

Reexamination Certificate

active

06934349

ABSTRACT:
There is disclosed a phase detector and phase locked loop circuit in which a maximum operation frequency is high. The phase detector of the present invention comprises three S-R flip-flops each of which comprises two NAND gates, a NAND gate connected to an input terminal of the S-R flip-flop, and an inverter. Even when a phase difference between a reference clock signal and a clock signal is large, UP and DOWN signals can be outputted in accordance with the phase difference between both signals, and therefore the maximum operation frequency can be set to be higher than that of a conventional phase detector.

REFERENCES:
patent: 4819081 (1989-04-01), Volk et al.
patent: 5705947 (1998-01-01), Jeong
patent: 58-164311 (1983-09-01), None
patent: 63-229912 (1988-09-01), None
patent: 2000-13222 (1998-06-01), None

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