Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1994-05-09
1996-05-28
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375376, 327156, H03D 324
Patent
active
055219470
ABSTRACT:
A phase-lock loop (PLL) includes a switch for opening the loop (e.g. for direct modulation of its voltage-controlled oscillator (VCO) during transmission of an intermittent signal such as data bursts) and has a phase comparator which can be selectively initialized (e.g. by setting to a programmed value or resetting to zero or terminal count value the reference and/or feedback signal frequency dividers) so that upon "re-closing" of the loop the PLL will achieve phase-lock within a predetermined amount of time. When the loop is opened, the VCO's dc ("phase-lock") control voltage can be maintained so as to help ensure that phase-lock will be achieved within the desired amount of time.
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Shigeki Saito et al., "State-Preserving Intermittently Locked Loop (Spill) Frequency Synthesiser for Portable Radio," IEEE Transactions on Microwave Theory and Techinques, vol. 37, No. 12 (Dec. 1989), pp. 1898-1903.
Supplemental Information Disclosure Statement including four declarations and exhibits A-D which were previously filed on Sep. 19, 1994, in U.S. patent application Ser. No. 08/029,134.
Bocure Tesfaldet
Chin Stephen
National Semiconductor Corporation
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