Phase correction for multiple processors

Details Phase correction for multiple processors Phase correction for multiple processors

2000-08-04

2004-11-09

Tran, Khai (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

06816561

ABSTRACT:

FIELD OF THE INVENTION
The invention generally relates to data processing with parallel processors and, more particularly, the invention relates to the phase correction of timing signals of parallel data processors.
BACKGROUND OF THE INVENTION
Two or more parallel data processors commonly are utilized to more rapidly process a relatively large amount of digital data. For example, parallel processors commonly are utilized within graphics accelerators to reduce the time required to perform the many calculations associated with rasterizing a display device.
In many multi-processor data processor architectures, parallel processors cooperate by synchronizing their timing signals including both the phase and frequency of the timing signals. One known method of synchronizing timing signals utilizes an external clock that generates a master clock signal for simultaneous use by each processor. Often, however, each processor in the multi-processor data processor architecture will modify the frequency of the master clock signal. The modification of the master clock signal may be necessary because, for example, the master clock frequency is faster than the processor to processor communication frequency. As a result of this modification, it is possible for the modified timing signals of each processor to have identical frequencies but different phases. This is illustrated in
FIG. 1
, which shows an example of a master clock signal
10
and the possible modified clock signals which can be obtained by dividing the master clock signal frequency in half (f/2). Half frequency clock
12
and half frequency clock
14
are 180° out of phase. Therefore, if each processor in the multi-processor system reduced the frequency of the master clock signal by half to produce a timing signal, it is possible for each processor to have a timing signal either in phase or 180° out of phase with respect to any other processor. In order to coordinate their respective processing tasks, however, each processor should have a timing signal with an identical frequency and phase.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, an apparatus for processing data includes a first processor which receives a source clock signal and converts the source clock signal to a first timing signal with a first phase and a second processor which receives the source clock signal and converts the source clock signal to a second timing signal with a second phase. A first phase correction circuit is coupled to the first processor and the second processor, the phase correction circuit determining whether the first phase is equivalent to the second phase. If the first phase and the second phase are not equivalent, the first processor modifies the first phase so that the first phase and the second phase are equivalent.
In a preferred embodiment, the difference between the first phase and the second phase is determined by transmitting a first phase correction signal from the first processor to the second processor via the first phase correction circuit and transmitting the first phase correction signal from the second processor back to the first processor via the first phase correction circuit. The difference between the first phase and the second phase may be determined by the total transmission time for the first phase correction signal. In a preferred embodiment, the first processor modifies the first phase by inverting the first timing signal. Alternatively, the first processor may modify the first phase by adding a clock delay to the first timing signal.
In accordance with another preferred embodiment, the apparatus further includes a third processor that receives the source clock signal and converts the source clock signal to a third timing signal with a third phase and a second phase correction circuit coupled to the second processor and the third processor. The second phase correction circuit determines whether the second phase is equivalent to the third phase. If the second phase and the third phase are not equivalent, the second processor modifies the second phase and the third phase such that the second phase and the third phase are equivalent.


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