Phase control signals for clock recovery circuits

Details Phase control signals for clock recovery circuits Phase control signals for clock recovery circuits

1999-09-27

2002-12-24

Corrielus, Jean (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S012000, C331S025000

Reexamination Certificate

active

06498824

ABSTRACT:

BACKGROUND OF THE INVENTION
a. Field of the Invention
The present invention relates to electronic circuits. More specifically, the present invention relates to data capture and clock recovery.
b. Background Information
Phase detectors and phase locked loops may be used in integrated circuits for clock synchronization and recovery of serial data streams. Because of variations in the fabrication process, operating temperatures, power supply levels, and interconnection routings, individual clock delays may be different from one integrated circuit to the next. These differences may create a clock skew between each integrated circuit and a system clock or serial data stream. Clock skew may significantly degrade system performance and may make it difficult to synchronize an individual edge with the system clock edge.
To minimize clock skew and achieve synchronization, a phase locked loop (PLL) may be used to track the system clock or incoming serial data stream, compare it with an on-chip clock, detect any phase or frequency difference, and then make any necessary adjustments to the on-chip clock until the on-chip clock matches the system clock. When this occurs, the phase locked loop may be “locked-on” to the system clock. After every integrated circuit in the system is synchronized with the system clock, the entire system may work in unison. If the operating conditions in the system should change, such as a temperature increase that degrades performance, the PLL may continue to track the system clock to restore normal operation.
A typical PLL may include a phase detector, a charge pump, a loop filter, and a voltage control oscillator (VCO). One type of phase detector is known as “bang-bang” phase detector. This technique uses a two times oversampling technique to detect phase error. In a bang-bang phase detector, the data stream may be sampled twice: once at the optimal sampling point, known as the center of the eye, and again as data switches to a different logic level, known as the edge transition. In other words, for data comprising one bit sent every nanosecond, the one bit may be sampled twice per nanosecond. By comparing the data sampled at the center of the eye with the data sampled as the data is switching, a determination may be made as to whether the system clock is leading or lagging the switch point of the data (here, the edge transition).
If the sampled data is different than the value sampled during the prior transition, i.e., during the prior edge transition, then the edge transition sample is made before the data changes to its new value. Thus, the system clock is leading. In this case, the phase detector generates a down signal to decrease-the speed of the system clock. Likewise, if the sampled data is different than the value sampled during the following edge transition, then the clock is lagging. Here, the phase detector generates an up signal to increase the speed of the system clock.
This bang-bang determination may be used to tune an oversampling clock to occur exactly as the data is switching. Since the data-sampling clocks occur between each oversampling clock (in the middle), a sample may be guaranteed of the exact center of the eye. However, a problem with this bang-bang phase detector is that the up and down control signals generated by the phase detector take a relatively long time to be validated, making the clock recovery circuit harder to stabilize.


REFERENCES:
patent: 5455540 (1995-10-01), Williams
patent: 5633899 (1997-05-01), Fiedler et al.
patent: 6072337 (2000-06-01), Dalmia et al.
patent: 6081572 (2000-06-01), Filip
patent: 6225831 (2001-05-01), Dalmia et al.

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