Phase comparing circuit and PLL circuit

Details Phase comparing circuit and PLL circuit Phase comparing circuit and PLL circuit

1995-07-20

1996-11-19

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375374, 375376, 327 3, 327 7, 327 12, 331 11, 331 25, H03D 324

Patent

active

055770797

ABSTRACT:
A phase comparing circuit includes a first device for generating a detection signal in response to a multi-level signal. The detection signal represents whether or not the multi-level signal is in a given level. A second device connected to the first device is operative for generating a first control signal in response to the detection signal generated by the first device and a clock signal. The first control signal represents a time interval between a leading edge of a pulse in the detection signal and a strobe point of the clock signal which immediately follows the leading edge of the pulse in the detection signal. A third device connected to the first device is operative for generating a second control signal in response to the detection signal generated by the first device and the clock signal. The second control signal represents a time interval between the strobe point of the clock signal and a trailing edge of the pulse in the detection signal. A fourth device connected to the second device and the third device for generating a phase error signal in response to the first control signal generated by the second device and the second control signal generated by the third device. The phase error signal represents a difference between a phase of the detection signal generated by the first device and a phase of the clock signal.

REFERENCES:
patent: 4280099 (1981-07-01), Rattlingourd
patent: 4977461 (1990-12-01), Ichimura

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