Phase comparator operable at half frequency of input signal

Details Phase comparator operable at half frequency of input signal Phase comparator operable at half frequency of input signal

1998-10-07

2001-11-06

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S159000, C331S00100A

Reexamination Certificate

active

06314151

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase comparator for use in a digital phase locked loop (PLL) circuit.
2. Description of the Related Art
In a serial communication system, in order to surely receive a serial input signal, synchronization between the serial input signal and a clock signal has to be established in a receiver circuit.
Generally, a digital serial input signal such as a Non Return to Zero (NRZ) signal latently includes a clock signal component which is produced when transmitting the digital serial signal. Therefore, the above-mentioned clock signal is recovered by a PLL circuit using the serial input signal.
A PLL circuit is usually constructed by a phase comparator for comparing the phase of an input signal with the phase of a clock signal, a loop filter for generating a control voltage in accordance with the output signal of the phase comparator, and a voltage controlled oscillator for controlling the frequency of the clock signal in accordance with the control voltage.
In a first prior art PLL circuit for recovery of a clock signal from a serial signal, the frequency of a clock signal is about the same as that of the NRZ signal (see: Charles R. {dot over (H)}odge, Jr., “A Self Correcting Clock Recovery Circuit”, IEEE Transactions on Elecron Devices, Vol. ED-32, No. 12, pp. 2704-2706, December 1985). This will be explained later in detail.
In the above-described first prior art PLL circuit, in order to increase the amount of transmitted data in a serial communication system, the transmission speed of data needs to be increased, which also increases the frequency of the clock signal. However, if the frequency of the clock signal is increased, the performance of a semiconductor device for transmitter/receiver circuits, particularly, the PLL circuit thereof has to be improved. This increases the manufacturing cost.
In a second prior art PLL circuit for recovery of a clock signal from a serial signal, multiple phased clock signals each having a smaller frequency than that of the serial signal are adopted. Therefore, the speed of transmitted data can be increased without the necessity of improving the semiconductor device for the PLL circuit (see: Chik.Kong Ken Yang et al., “A 0.8&mgr;m CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 12, December 1996).
In the above-mentioned prior art PLL circuit, however, if the number of the multiple phased clock signals is increased, it is difficult to accurately control the multiple phased clock signals, and also, a circuit configuration for the multiple phased clock signals is increased in size, which further increases the power dissipation.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a PILL circuit, particularly, a phase comparator thereof capable of decreasing the size and the power dissipation thereof without the necessity of improving the performance of a semiconductor device therefor.
According to the present invention, in a phase comparator, a first data fetching circuit fetches an input signal in response to a transition timing of a clock signal having a frequency about half that of the input signal, and a second data fetching circuit fetches the output signal of the first data fetching circuit in response to a transition timing of an inverted signal of the clock signal. A first exclusive OR performs an exclusive OR operation upon the input signal and the output signal of the first data fetching circuit, and a second exclusive OR circuit performs an exclusive OR operation upon the output signals of the first and second data fetching circuits. An inverter inverts the output signal of the first exclusive OR circuit. A first AND circuit performs an AND operation upon the output signal of the second data fetching circuit and the output of the exclusive OR circuit, a second AND circuit performs an AND operation upon the output signal of the first exclusive OR circuit and the output of the first AND circuit to generate a leading signal, and a third AND circuit performs an AND operation upon the output signal of the inverter and the output of the first AND circuit to generate a lagging signal.
Thus, since the frequency of the clock signal is decreased, it is unnecessary to improve the performance of a semiconductor device for a PILL circuit.


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Chin-Kong Ken et al., “A 0.8-&mgr;m CMOS 2.5Gb/s Oversampling Receiver and Transmitter for Serial Links”, IEEE Journal of Solid State Circuits, vol. 31, No. 12, pp. 2015-2023, Dec. 1996.

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