Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements
Patent
1987-07-17
1989-02-21
Laroche, Eugene R.
Oscillators
Automatic frequency stabilization using a phase or frequency...
Afc with logic elements
331DIG2, H03L 700, H03L 706
Patent
active
048068780
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention concerns improvements in or relating to phase comparator lock detect circuits and synthesisers using the same. More particularly, it relates to an in-phase-lock detect circuit suitable for use in a digital phase-lock-loop synthesiser of the kind which comprises a phase comparator responsive to a reference frequency and to a frequency derived via a variable divider from a variable frequency oscillator (VFO) for providing frequency `up` and frequency `down` error signals and a loop amplifier responsive to these error signals and by which means a control signal is fed to the VFO, to control the frequency thereof.
The invention has application to frequency synthesis circuit design in general, and to UHF/VHF heterodyne tuning circuits in particular.
BACKGROUND ART
In television receivers, and the like, it is common practice to employ a digital phase-lock-loop (PLL) frequency synthesiser as part of the front-end tuning circuit. It is a problem, in these receivers, that tuning can be relatively coarse, especially where the implementation is of a low-cost simple construction.
Also due to component drift with ageing the comparison reference frequency may drift or become noisy so causing errors in the synthesised local oscillator frequency.
A further problem arises with these systems when they are used to demodulate r.f. signals from a low quality source, where the actual frequency may be time dependant.
A known improvement upon the aforesaid incorporates a combination of digital and analogue control circuits, employed in tandem. In this arrangement the local oscillator frequency is controlled by a digital P.L.L. until it comes within capture range of the analogue circuit. Subsequently, the variable frequency oscillator is controlled by the latter circuit. A lock detect circuit has been used thus to monitor the performance of the digital PLL and to transfer control to the analogue circuit once `in-lock` has been attained.
Hitherto, such lock-detect circuits have not been without shortcomings. In particular, such lock detect circuits used in phase comparators can be inherently poor indicators of lock being achieved since in general they:
(i) do not accurately define the lock window;
(ii) in variable reference frequency (f ref) systems the actual lock varies with f ref;
(iii) they are prone to producing spurious `in-lock` signals when the system is in fact out of lock unless external circuitry (hence extra device pins) is used to correct this fault;
(iv) Analogue lock detect circuits are inherently complex in their operation and also require external components, and,
(v) in some digital systems the lock window is highly process dependant.
DISCLOSURE OF THE INVENTION
The present invention is intended to obviate the above shortcomings. It shall prove advantageous in that
(i) it has an accurately defined lock window;
(ii) the lock window can be designed to be independant of f ref;
(iii) under normal operating conditions, it can be designed so as not to produce spurious `in lock` signals;
(iv) it will not require any external circuitry; and
(v) the lock window is process independant.
It is observed that in the digital phase-lock-loop synthesiser of the kind aforesaid, when phase-lock condition is obtained, frequency `down` signals, only, are produced to compensate for leakage current in the loop amplifier and these will be of known magnitude to compensate for leakage current in the loop amplifier. As discussed herein, the frequency `up` and the frequency `down` signals are thus monitored by a logic circuit to detect this particular condition and to provide an `in lock` indication signal.
In accordance with the present invention there is thus provided a phase comparator lock detect circuit, for use in a digital synthesiser of the kind aforesaid, this circuit including logic gates responsive to the frequency `up` and frequency `down` signals during a predetermined period derived in dependance upon signal fed to the phase comparator from the variable divider, the gates being arran
REFERENCES:
patent: 4122405 (1978-10-01), Tietz et al.
patent: 4290029 (1981-09-01), Streckenbach
patent: 4437072 (1984-03-01), Asami
patent: 4473805 (1984-09-01), Guhn
LaRoche Eugene R.
Mis David
Plessey Overseas Limited
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