Phase comparator having a flip-flop circuit and a logic circuit

Details Phase comparator having a flip-flop circuit and a logic circuit Phase comparator having a flip-flop circuit and a logic circuit

2008-06-10

2008-06-10

Kim, Kevin (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S326000

Reexamination Certificate

active

07386083

ABSTRACT:
A phase comparator has a flip-flop circuit and a logic circuit. The flip-flop circuit compares an input clock signal with a leading edge and a trailing edge of an input data signal to produce a leading phase comparison result signal indicative of a leading phase comparison result related to the leading edge of the input data signal and a trailing phase comparison result signal indicative of a trailing phase comparison result related to the trailing edge of the input data signal. The logic circuit produces an output up signal when both of the leading and the trailing phase comparison result signals indicate a lag phase of the input clock signal. The logic circuit produces an output down signal when both of the leading and the trailing phase comparison result signals indicate a lead phase of the input clock signal.

REFERENCES:
patent: 3614635 (1971-10-01), LaPine et al.
patent: 5237554 (1993-08-01), Senshu et al.
patent: 6236696 (2001-05-01), Aoki et al.
patent: 6249188 (2001-06-01), Kaneko
patent: 6-132817 (1994-05-01), None
patent: 10-22799 (1998-01-01), None
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patent: 2001-144592 (2001-05-01), None
J. Savoj et al., “5.3 A 10Gb/s CMOS Clock and Data Recovery Circuit with Frequency Detection”, ISSOC 2001/Session 5/Gigabit Optical Communications I/5.3.

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