Phase comparator for determining in which direction the...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Utility Patent

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C375S376000, C327S147000

Utility Patent

active

06169774

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase comparator advantageously for use in phase-locked loops.
2. Description of the Background Art
As well known in the art, the phase comparator, particularly for use in the phase-locked loop (PLL), is one of the most important electronics components which are employed in a greater amount in the electronics appliances, such as telecommunications devices. For telecommunications devices, crystal oscillators were traditionally used in order to accurately control the frequency and the phase of signals to be transmitted and received. The tendency of designing increasing channels to be multiplexed for transmission caused the crystal oscillators to be increased included in the telecommunications devices, thus giving rise to increasing the mass and the cost of the devices.
The difficulties described above were overcome by the PLL circuits. As known, the PLL circuit includes, in addition to a crystal oscillator, a self-controlled, own oscillator for generating a reference freqeuency. The phase comparator is one of the constituent components forming the PLL loop, and adapted to determine the phase difference of the signal generated by the PLL loop from a reference signal generated by the crystal oscillator. In response to the phase difference determined, controlled are the frequency and the phase of the signal generated by the PLL loop. Under the locked condition, namely, the accurately controlled condition, from the output of the PLL loop, obtained is a signal which precisely follows the reference signal which the crystal oscillator stably generates.
With the PLL circuits including the conventional phase comparator involve the problem to be solved which is caused by the phase comparison range within which the phase comparator is adapted to compare the phases between a reference signal and an oscillating signal. More specifically, the phase comparison range is in principle restricted within the period of one cycle of the oscillating signal, so that an abrupt increase of the oscillating frequency does not allow the PLL circuit to follow the corresponding phase difference. The problem has been overcome by designing the PLL loop such that the oscillating frequency to be compared is divided into a lower frequency, which is in turn compared with a reference frequency. That caused the circuitry for frequency divider to be more bulky and consume more electric power.
An example of the PLL circuit including such a frequency divider is described in co-pending U.S. patent application Ser. No. 08/714,269 assigned to the same assignee as that of the present invention. The U.S. application discloses bit phase synchronizing circuitry which includes a timing decision circuit for receiving data with an unknown phase and triphase clocks generated from a reset voltage-controlled oscillator (VCO). If preselected one of the triphase clocks and the received data have an adequate relation therebetween, then the decision circuit causes the current clock phase to be maintained, or, otherwise, determines whether the current clock phase should be advanced or restarted. Outputs from a multiplication PLL circuit are selectablly supplied to the reset VCO in response to the decision circuit. The decision circuit latches the received data with the preselected one triphase clock and produces the data together with the clock used for latching. A phase control causes the reset VCO to selectively operate in a phase shift mode or in a multiplication PLL mode. That causes bit phase synchronization to be set up stably.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a phase comparator which allows a phase-locked loop to be locked even with an abrupt change over a period of time exceeding one cycle of an oscillating frequency without increasing a substantive amount of circuitry.
In accordance with the present invention, a phase comparator for comparing a phase of a subject signal with a phase of a reference signal for producing a result signal representative of a result therefrom, comprising: a first phase shifter for advancing the phase of the subject signal by a predetermined angle to produce a first signal, the predetermined angle being substantially equal to &pgr;/4; a second phase shifter for delaying the phase of the subject signal by the predetermined angle to produce a second signal; a first phase comparator circuit for comparing a phase of the first signal with the phase of the reference signal during a plurality of periods of the reference signal or the first signal to obtain a phase difference in each of the plurality of periods to produce a first phase difference signal representative of the phase difference obtained; a second phase comparator circuit for comparing a phase of the second signal with the phase of the reference signal during a plurality of periods of the reference signal or the second signal to obtain a phase difference in each of the plurality of periods to produce a second phase difference signal representative of the phase difference obtained; a decision circuit operative in response to the first and second phase difference signals for determining whether the phase of the subject signal changes in a first direction in which the phase difference increases or in a second direction in which the phase difference decreases; and a reversible counter operative in response to said decision circuit for incrementing or decrementing a count to produce the result signal corresponding to the count.


REFERENCES:
patent: 5430773 (1995-07-01), Marbot
patent: 5548235 (1996-08-01), Marbot
patent: 5877641 (1999-03-01), Ziegler et al.
U.S. Patent Application No. 08/714,269 (Nobusuke Yamaoka et al.).

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