Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2007-08-14
2007-08-14
Kumar, Pankaj (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
Reexamination Certificate
active
10391298
ABSTRACT:
A phase comparator comprises a latch unit for latching the input data signal in parallel on rising/falling edges of the respective clock signals respectively, an error signal output unit for outputting m error signals respectively indicative of differences in phase between the transient edge of the input data signal and the transient edges of the respective clock signals and each having a minimum pulse width of (m/2−1)×T or more, based on respective output signals produced from the latch unit and the respective clock signals, an input unit for inputting the respective output signals produced from the latch unit in parallel on the rising/falling edges of the respective clock signals and a reference signal output unit for outputting m reference signals whose pulse widths are (m/2)×T, based on output signals produced from the input unit and the respective clock signals.
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J. Savoj et al., “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector”, IEEE Journal of Solid-State Circuits, vol. 36, No. 5, May 2001, pp. 761-768.
Kumar Pankaj
NTT Electronics Corporation
Rothwell, Figg, Ernst and Manbeck, P.C.
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