Phase comparator circuit

Details Phase comparator circuit Phase comparator circuit

2005-09-13

2005-09-13

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C307S402000

Reexamination Certificate

active

06944252

ABSTRACT:
A data signal DATA is captured by flip-flops10and11alternately every half cycle time of a clock signal CLK, outputs of the flip-flops10and11are delayed by respective delay circuits15and16to generate delayed signals10QD and11QD, and an output of the flip-flop10and the delayed signal11QD are provided to an XOR gate18, while an output of the flip-flop11and the delayed signal10QD are provided to an XOR gate17. The delay times of the delay circuits may be variable. Furthermore, outputs of the XOR gates17and18may be captured by the respective flip-flops alternately every half-cycle time of a delayed clock signal obtained by delaying the clock signal CLK.

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