Phase coefficient generation for PLL

Details Phase coefficient generation for PLL Phase coefficient generation for PLL

2007-03-19

2011-10-18

Ha, Dac (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S371000, C375S357000, C375S373000, C327S151000, C370S503000

Reexamination Certificate

active

08040994

ABSTRACT:
A method and apparatus is provided for synchronizing a clock signal by generating time varying PLL phase coefficients which approximate optimal PLL phase coefficients. An acquisition mode phase coefficient is determined by adding an error signal (A) to the sample counter (k) and finding the reciprocal of the result (1/(A+k)). The reciprocal can be calculated in hardware or determined by using a lookup table. A tracking mode phase coefficient is determined based on the error signal for use in the PLL during a track a tracking period. The tracking period begins when the tracking mode coefficient is greater than the acquisition mode coefficient.

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