Phase-change multi-level cell and operating method thereof

Static information storage and retrieval – Systems using particular element – Amorphous

Reexamination Certificate

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C365S148000

Reexamination Certificate

active

07106623

ABSTRACT:
A phase-change multi-level memory cell is described, including a semiconductor substrate, a gate structure, two S/D regions, and two phase-change storing units electrically connected to the two S/D regions respectively. One phase-change storing unit can be programmed to one of many phases having different electrical resistances, and combination variations of the phases of the two phase-change storing units generate different read currents corresponding to 2nn-bit data values (n≧2). To program the cell, the phase of each phase-change storing unit is changed to one of the many phases mentioned above, so that the phase combination of the two phase-change storing units corresponds to a predetermined data value. In addition, when reading the memory cell, the read current is measured to obtain the data value stored.

REFERENCES:
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patent: 5912839 (1999-06-01), Ovshinsky et al.
patent: 6750469 (2004-06-01), Ichihara et al.
patent: 6757190 (2004-06-01), Lowrey
patent: 6759267 (2004-07-01), Chen
patent: 6813177 (2004-11-01), Lowrey et al.

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