Phase change memory with bipolar junction transistor select...

Details Phase change memory with bipolar junction transistor select... Phase change memory with bipolar junction transistor select...

2007-12-31

2010-12-07

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Resistive

C365S163000, C365S230030

Reexamination Certificate

active

07848133

ABSTRACT:
A phase change memory may be organized with a global word line coupled to a plurality of blocks, each with a plurality of phase change memory cells arranged in rows and columns. Thus, one global word line may be common to a plurality of blocks. The global word line may be coupled to a word line decoder that is responsible for pulling the word line to ground. Each of the blocks, on the other hand, is coupled to a bitline selector through a bitline. Each block may have its own local word line coupled to the global word line. In some cases, this architecture reduces the minimum capacity of the memory.

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