Phase change memory device

Details Phase change memory device Phase change memory device

2006-05-23

2006-05-23

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Amorphous

C365S154000

Reexamination Certificate

active

07050328

ABSTRACT:
A phase change memory has an array formed by a plurality of cells, each including a memory element of calcogenic material and a selection element connected in series to the memory element; a plurality of address lines connected to the cells; a write stage and a reading stage connected to the array. The write stage is formed by current generators, which supply preset currents to the selected cells so as to modify the resistance of the memory element. Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

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Hwang, Y. et al., “Completely CMOS-Compatible Phase-Change Nonvolatile RAM Using NMOS Cell Transistors,” inProceedings of the Non-Volatile Semiconductor Memory Workshop NVMW 2003, Monterey, CA., Feb. 16-20, 2003, pp. 91-92.

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