Phase change memory array having equalized resistance

Static information storage and retrieval – Systems using particular element – Resistive

Reexamination Certificate

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C365S063000, C365S163000

Reexamination Certificate

active

07339814

ABSTRACT:
A memory includes memory cells, a first line coupled to the memory cells, and a second line coupled to the memory cells. A series resistance due of the first line plus the second line at each one of the memory cells is substantially equal.

REFERENCES:
patent: 5825683 (1998-10-01), Chang
patent: 6456525 (2002-09-01), Perner et al.
S. J. Ahn et al., “Highly Manufacturable High Density Phase Change Memory of 64Mb and Beyond”, IEDM 2004.
H. Horii et al., “A Novel cell technology using N-doped GeSbTe films for phase change RAM”, VLSI, 2003.
Y. N. Hwang et al., “Full Integration and reliability evaluation of phase-change RAM based on 0.24μm-CMOS technologies”, VLSI, 2003.
S. Lai et al., “OUM-a 180 nm nonvolatile memory cell element technology for stand alone and embedded applications”, IEDM 2001.
Y. H Ha et al., “An edge contact type cell for phase change RAM featuring very low power consumption”, VLSI, 2003.
W. Y. Cho et al., “A 0.18 um 3.0-V 64-Mb nonvolatile phase transition random access memory (PRAM)”, IEEE J. Sol. State Circuits 40 (1), 293, 2005.
F. Bedeschi et al., “A 8Mb demonstrator for high density 1.8V Phase-change memories”, VLSI 2004.

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