Phase blender and multi-phase generator using the same

Details Phase blender and multi-phase generator using the same Phase blender and multi-phase generator using the same

2001-09-25

2003-09-09

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Combining of plural signals

C327S361000, C327S269000

Reexamination Certificate

active

06617909

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase blender and a multi-phase generator using the same, and more particularly to a phase blender for generating, by using input voltages having a phase difference, an output voltage corresponding to an intermediate phase, and a multi-phase generator for generating output voltages having an arbitrary phase difference by using the phase blender. The present application is based on Korean Patent Application No. 2001-8033, which is incorporated herein by reference.
2. Description of the Related Art
In order to realize the phase locked loop (PLL) or a delayed locked loop (DLL) as a clock generator using a phase blending mode, signals with diverse phases each delayed by a different amount are required to be inputted, or a phase blender which outputs various signals having a smaller phase difference than a phase difference of two inputted signals is required, as well as a multi-phase generator using such a phase blender.
It is referred to as “delay mixing” or “delay interpolation” to control a delay amount of an output signal with respect to two input signals having a delay difference, and an actual output signal is additionally delayed by a group delay of an entire system. In order to obtain such characteristics, an output signal may be generated by controlling a ratio of the current sources of two signals and adding the controlled ratio, and a fine-tap may be obtained by colliding two delayed signals using an inverter (related documents: B. W Garlepp et al., A portable digital DLL for high-speed CMOS interface circuit, IEEE J. Solid-state Circuits, vol. 34, pp.632-644, May 1999, and S. Sidiropoulos, High-performance interchip signaling, Ph.D. dissertation, Available as Tech. Rep. CLS-TR-98-760 from http://elib.stanford.edu Computer Systems Lab., Stanford University).
A phase blender inputs a selection code of N bits with respect to two inputs Vin
1
and Vin
2
having a delay time &Dgr;t and generates an output signal with the &Dgr;t divided by ½
N
. Accordingly, a signal with a minimum delay time should be outputted in case that an N-bit code is ‘0’, a signal with a maximum delay time should be outputted in case of 2
N
−1, and, in case that an arbitrary value between ‘0’ and ‘2
N
−1’, a signal with linear delay characteristics corresponding to the value should be outputted.
FIG. 1
shows a conventional phase blender. The phase blender shown in
FIG. 1
takes a mode that generates an output signal having an intermediate delay amount by using an output of a CMOS inverter. A detailed description will be as follows (that two signals contrasted have a phase difference means that the two have a time difference as large as and corresponding to the phase difference in a time domain, so the same meaning applies to the phase difference and the time difference).
To a phase blender
20
are inputted two input voltages Vin
1
and Vin
2
having a phase difference, and the phase blender
20
outputs three output voltages Vout
1
, Vout
2
, and Vout
3
having different phases from each other. The phase blender
20
has first and second phase delay units
21
and
22
to which the first and second input voltages Vin
1
and Vin
2
are respectively inputted, and an intermediate phase output unit
30
to which the first and second input voltages Vin
1
and Vin
2
are inputted. The first and second phase delay units
21
and
22
output the first and second output voltages having phases respectively corresponding to the phases of the first and second input voltages Vin
1
and Vin
2
, and the intermediate phase output unit
30
outputs a third output voltage Vout
3
having a phase corresponding to an intermediate phase of the first and second input voltages Vin
1
and Vin
2
.
The intermediate phase output unit
30
has a pair of first inverters
31
a
and
31
b
whose output ports are mutually connected and to which the first and second input voltages Vin
1
and Vin
2
are inputted, and a second inverter
32
for inputting the output voltages of the first and second inverters
31
a
and
31
b
and outputting a third output voltage Vout
3
. Further, the first phase delay unit
21
is constituted with a pair of third inverters
21
a
and
21
b
connected in series, and the second phase delay unit
22
is constituted with a pair of third inverters
22
a
and
22
b
connected in series.
A detailed circuit for each inverter shown in
FIG. 1
is shown in FIG.
2
. Each inverter includes a PMOS(MP0) transistor and an NMOS(MN0) transistor connected in series. The source of the PMOS(MP0) transistor is applied with a source voltage V
DD
, the source of the NMOS(MN0) transistor is grounded. Further, the drains of the PMOS(MP0) and NMOS(MN0) transistors are mutually connected. An input voltage Vin is respectively inputted to the gates of the PMOS(MP0) and NMOS(MN0) transistors, and an output voltage Vout is outputted from the drains, that is, from a connection portion of the PMOS(MP0) and NMOS(MN0) transistors. The PMOS(MP0) and NMOS(MN0) transistors operate as switches which are switched according to the input voltage Vin. At this time, a switching mode is the same as follows.
Vin
PMOS(MP0)
NMOS(MN0)
Vout
high
off
on
low
low
on
off
high
The PMOS(MP0) and NMOS(MN0) transistors are simply described, in the above table, to be turned on or off in operations, but the PMOS(MP0) and NMOS(MN0) transistors vary their resistance values according to a change of a magnitude of the input voltage Vin to operate as variable resistors varying from a short state (or an open state) to the open state (or a short state) substantially. Further, in view of the input voltage, a virtual capacitor C
0
is supposed to be connected to an input stage of the inverter.
FIG. 3
is a graph for showing a relationship between the input voltage and output voltages of the inverter shown in FIG.
2
. The input voltage Vin, based on the operations as shown in the table, is outputted as an output voltage with its phase inverted. At this time, the switching operations of the PMOS(MP0) and NMOS(MN0) transistors in the inverter are accompanied by a certain time delay, so that, as shown in
FIG. 3
, the phase-inverted output voltage Vout is outputted after a predetermined delay time.
FIG. 4
is a graph for showing a relationship of the inputs and outputs of a conventional phase blender as shown in FIG.
1
.
If the first input voltage Vin
1
is inputted to the first phase delay unit
21
, the first output voltage Vout
1
is outputted in the same waveform as in the first input voltage Vin
1
since the first phase delay unit
21
includes the two inverters
21
a
and
21
b
. At this time, a waveform delayed by a predetermined delay time by the two inverters
21
a
and
21
b
is outputted. With respect to the second input voltage Vin
2
, the second phase delay unit
22
outputs the second output voltage Vout
2
having the same waveform as the second input voltage Vin
2
but delayed by the delay time. Accordingly, the first and second phase delay units
21
and
22
output the first and second output voltages Vout
1
and Vout
2
having phases corresponding to the phases of the first and second input voltages Vin
1
and Vin
2
.
If the first and second input voltages Vin
1
and Vin
2
are inputted with a certain time difference &Dgr;t, the intermediate phase output unit
30
outputs the third output voltage Vout
3
lagged by ½ &Dgr;t compared to the first output voltage Vout
1
and preceded by ½ &Dgr;t compared to the second output voltage Vout
2
, which is a signal inverted at the intermediate point of the inverting points of the first and second input voltages Vin
1
and Vin
2
. At this time, the third output voltage Vout
3
has the same delay time as in the first and second output voltages Vout
1
and Vout
2
. Accordingly, the third output voltage Vout
3
is outputted which has a phase corresponding to an intermediate phase of the first and second input voltages Vin
1
and Vin
2
.
When modeling the above phase blender, under the assumptio

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