Phase and frequency detection circuits for data...

Oscillators – Automatic frequency stabilization using a phase or frequency... – With intermittent comparison controls

Reexamination Certificate

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C331S017000, C331S018000, C331S025000

Reexamination Certificate

active

11190323

ABSTRACT:
In one embodiment, a phase-locked loop system in a receiver samples received incoming data using a first clock and a second clock that have the same frequency but are out of phase with each other. A first control signal generated by a phase detector is used to control a charge pump, whose output may be filtered to drive a VCO circuit generating the first and second clocks. A frequency detector generates a second control signal based at least on phase relationships between the incoming data and the first and second clocks. A qualifier circuit determines if the first control signal is valid or invalid based at least on the second control signal. If the first control signal is invalid, the qualifier circuit prevents the first control signal from being used to adjust the frequency of the first and second clocks.

REFERENCES:
patent: 4535459 (1985-08-01), Hogge, Jr. et al.
patent: 5057793 (1991-10-01), Cowley et al.
Ansgar Pottbacker, et al., “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction Up to 8 Gb/s”, IEEE Journal of Solid-State Circuits, Dec. 1992, pp. 1747-1751, vol. 27, No. 12.
David G. Messerschmitt, “Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery”, IEEE Transactions on Communications, Sep. 1979, pp. 1288-1295, vol. COM-27, No. 9.

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