Phase and delay locked loops and semiconductor memory device...

Details Phase and delay locked loops and semiconductor memory device... Phase and delay locked loops and semiconductor memory device...

2005-10-25

2008-03-04

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S008000, C331S025000, C327S157000, C327S158000

Reexamination Certificate

active

07339438

ABSTRACT:
A phase locked loop includes a phase difference detector for detecting a phase difference between an input clock signal and an output clock signal to generate an up signal and a down signal; a charge pump for raising a level of a control signal by supplying a supply current in response to the up signal, for lowering a level of the control signal by discharging a discharge current in response to the down signal, and for adjusting the supply current in response to a first control voltage and by discharge current in response to a second control voltage in a locked state; a compensator for generating the first and second control voltages corresponding to difference between the up signal and the down signal in the locked state; and a voltage controlled oscillator for varying a frequency of the output clock signal in response to the control signal.

REFERENCES:
patent: 5831483 (1998-11-01), Fukuda
patent: 6043715 (2000-03-01), Bailey et al.
patent: 6779126 (2004-08-01), Lin et al.
patent: 2001-0050937 (2001-06-01), None
patent: 2001-92529 (2001-10-01), None
patent: 2003-0028312 (2003-04-01), None
English language abstract of Korean Publication 2001-0050937.
English language abstract of Korean Publication 2001-92529.
English language abstract of Korean Publication No. 2003-0028312.

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