Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1997-09-16
2001-04-17
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S156000
Reexamination Certificate
active
06219395
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to circuits and methods for phase alignment of frames in computer telephony busses.
BACKGROUND OF THE INVENTION
Computer telephony is based on digital communication across time division multiplexed serial data lines, known as “streams.” A typical computer telephony bus provides 16 or more streams, which each have between 32 and 128 timeslots. The timeslots in the streams all occur at the same time because the streams are synchronized with reference to a single bit called the “frame pulse.”
Circuits that interface with the bus must also be synchronized to the clocks present on the bus to ensure that the data transferred between the circuit and the bus have the same frequency as the data on the bus. But frequency lock does not ensure that the timeslots in the bus are lined up with events in interface. In such a situation, the interface frame and the bus frame are considered to be “frequency locked, but not phase aligned.”
Upon power-up and initialization of an entire system, an interface circuit that interfaces with the bus, such as a digital switch, will generally be both frequency locked and phase aligned. During the course of operation, however, it is possible for a new clock circuit to assume the role of “master,” and take on the role of establishing the clocking and frame synchronization. When this happens, the circuit may remain frequency locked, relative to the new clock master but lose phase alignment. It is possible to reinitialize the circuit to again achieve synchronization, but this can take time and result in data loss.
SUMMARY OF THE INVENTION
In one general aspect, the invention features a communication bus interface circuit that includes a local frame signal generator responsive to a device clock signal and having a local bus frame signal output. A synchronization loss detector is responsive to the local frame signal output and to a bus frame signal input, and a clock adjuster is responsive to the synchronization loss detector and to the device clock signal to adjust the local frame signal generator until synchronization between the bus frame signal and the local frame signal is established.
In preferred embodiments, the clock adjuster includes output lines for providing an add or a subtract signal or both an on/off and an add/subtract signal to the local bus frame signal generator. The clock adjuster can include an offset measurement circuit responsive to the bus frame signal input and to the local frame signal output for measuring a timing difference between the bus frame signal and the local frame signal and the local frame signal generator can operate by either adding a clock cycle to the device clock or subtracting a device clock cycle from the local frame signal length depending on the measure of the timing difference. The clock adjuster can be constructed and adapted to adjust the clock over several bus frame signal periods, the local bus frame signal generator can also be responsive to a power-up reset circuit, and the clock generation circuit can include a counter having a load input and an enable input responsive to the clock adjuster.
In another general aspect, the invention features a bus frame signal input and a local frame signal generator having a local frame signal output. A synchronization loss detector is responsive to the local bus frame signal output of the bus frame signal generator and to the bus frame signal input, and a frame signal length modulator is responsive to the synchronization loss detector for causing the local frame signal generator to adjust the length of the local frame signal on its local frame signal output until synchronization between the bus frame signal input and the local frame signal is established.
In preferred embodiments, the modulator includes an output line for providing an add signal to the local bus frame signal generator to shorten the local bus frame signal, or the modulator includes an output line for providing a subtract signal to the local bus frame signal generator to lengthen the local bus frame signal. The modulator can include an offset measurement circuit responsive to the bus frame signal input and to the local frame signal for measuring a timing difference between the bus frame signal and the local frame signal and the local frame signal generator can provide either an add signal or a subtract signal to the local bus frame signal generator depending on the measure of the timing difference. The local bus frame signal generator can also be responsive to a power-up reset circuit.
In a further general aspect, the invention features a communications bus interface method that includes receiving a bus frame signal, generating a local frame signal output based on the bus frame signal, detecting a loss of synchronization between the bus frame signal and the local frame signal, and modulating the length of the local frame signal to establish synchronization between the bus frame signal and the local frame signal over several local bus frame signal periods.
In preferred embodiments, the step of adjusting the device clock signal operates by adding or subtracting a device clock cycle from a device clock signal. The method can also include detecting a measure of a timing difference between the bus frame signal and the local frame signal and the step of modulating can operate by either adding a device clock cycle to the local frame signal length or subtracting a device clock cycle from the local frame signal length depending on the measure of the timing difference.
Systems according to the invention can be advantageous in that they may permit a circuit that interfaces with the bus to return to phase alignment while minimizing data errors. Since a fraction of a bit time, such as a single cycle of a device clock, is removed or added from the frame length in one frame time, the frames can align gradually. This can take place faster than if the interface circuit were to be reset altogether, and can reduce or eliminate the side effects of communications errors. This is particularly important in low-latency systems which carry audio, video, or other time-sensitive information.
REFERENCES:
patent: 4546486 (1985-10-01), Evans
patent: 4573017 (1986-02-01), Levine
patent: 4972442 (1990-11-01), Steierman
patent: 5040190 (1991-08-01), Smith et al.
patent: 5668830 (1997-09-01), Georgion et al.
Linton Charles C.
Pollack Jonathan D.
Hunter Shane H.
Mintz Levin Cohn Ferris Glovsky and Popeo PC
Natural MicroSystems Corp.
Pham Chi
Tran Khai
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