Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-05-05
2008-03-11
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07343575
ABSTRACT:
A method for functional verification includes transforming an original multiphase circuit design into a phase-abstracted circuit design by identifying cyclical (repetitive) signals in the multiphase circuit design, determining a number of simulation phases for the multiphase circuit design, unwinding the multiphase circuit design by the number of phases to create an unwound design, and then applying logic reduction techniques to the unwound design using the clock-like signals to reduce (simplify) the logic in the unwound design by eliminating unused/unnecessary registers, inputs, outputs, and logic. The resulting phase-abstracted design can then be processed much more efficiently by functional verification engines than the original multiphase circuit design due to the reduced number of registers/inputs.
REFERENCES:
patent: 5646796 (1997-07-01), Kimura et al.
patent: 2003/0192018 (2003-10-01), Baumgartner et al.
patent: 2006/0212837 (2006-09-01), Prasad
Baumgartner et al. “Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists,” Computer Aided Verification, 1999, 12 pages.
Hasteer et al. “Efficient Equivalence Checking of Multi-Phase Designs Using Phase Abstraction and Retiming,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 3, No. 4, Oct. 1998, pp. 600-625.
Bjesse Per
Kukula James H.
Bever Hoffman & Harms LLP
Dinh Paul
Harms Jeanette S.
Synopsys Inc.
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