Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-31
2007-07-31
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10994858
ABSTRACT:
Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing of an action by aggressors that occur during a region (209, 319, 321) where victim and aggressor timing windows overlap and determines an effective delta delay317corresponding to any portion316of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty (627, 637) in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time607, 613, i.e. during a switching time window (a2to a2+u1) (613, 625) when uncertainty is included.
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Algor Ilan
Becer Murat R.
Grinshpon Amir
Levy Rafi
Oh Chanhee
Bethards Charles W.
Freescale Semiconductor Inc.
Whitmore Stacy A
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