Static information storage and retrieval – Read/write circuit – Testing
Patent
1995-01-03
1997-05-06
Nguyen, Viet Q.
Static information storage and retrieval
Read/write circuit
Testing
36523006, 36518909, G11C 700, G11C 2900
Patent
active
056277873
ABSTRACT:
According to the method of the present invention, stress testing of decoders and other periphery circuits of synchronous RAMs is performed within a reasonable period of time and without an increase in the complexity of stress testing or fabrication of synchronous RAMs. In order to stress test decoders and periphery circuits of a synchronous RAM to obtain maximum fault coverage of possible latent defects, a periphery stress mode is defined through appropriate manipulation of the Power-On Reset signal of the device such that all nodes of a memory array of the synchronous RAM are pulled in the opposite logic state from that required for a memory cell stress mode. In the periphery stress mode, the Power-On Reset signal is allowed to pulse upon power-up of the synchronous RAM device such that latches and flip flops of the device are forced in a logic state that disables all rows and columns of the memory array of the device. Additionally, all D.C. (direct current) paths of the synchronous RAM are disabled so that a high power supply voltage may be applied during the periphery stress mode without fear of transistor "snap back voltage". Thus, once all D.C. paths of the synchronous RAM are disabled, a Vcc voltage level as high as ten volts may be applied during the periphery stress mode without experiencing transistor impact ionization due to high substrate current, known as BVDII or "snap back voltage".
REFERENCES:
patent: 5287312 (1994-02-01), Okamura et al.
patent: 5341336 (1994-08-01), McClure
patent: 5357193 (1994-10-01), Tanaka et al.
patent: 5379260 (1995-01-01), McClure
patent: 5424988 (1995-06-01), McClure
patent: 5455799 (1995-10-01), McClure et al.
Galanthay Theodore E.
Jorgenson Lisa K.
Larson Renee M.
Nguyen Viet Q.
SGS-Thomson Microelectronics Inc.
LandOfFree
Periphery stress test for synchronous RAMs does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Periphery stress test for synchronous RAMs, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Periphery stress test for synchronous RAMs will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2137847