Peripheral unit having at least two sequencer circuits configure

Electrical computers and digital processing systems: support – Computer power control – Power conservation

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Details

713322, 713323, 713330, 710 8, G06F 132

Patent

active

060165499

ABSTRACT:
It is the object of the present invention to provide an improved peripheral unit, incorporating an MPU, that can reduce power consumption appropriately in accordance with mode transition when a host command from a host computer system is being processed, and a control method therefor. An MPU that requires a large amount of power, for example, is activated only when necessary, such as for the processing of a command (host command) from a computer system (host), and is deactivated during all other periods, by relinquishing the right of controlling of the operations to the respective sequencer circuits. The first sequencer circuit is activated only when necessary, such as for the transfer of data to the computer system. For the hardware operation of a device (e.g., writing data to or reading data from the device), the first sequencer circuit is deactivated, relinquishing the control right of that operation to the second sequencer circuit. On the other hand, for the transfer of data to the computer system, the second sequencer circuit is deactivated, relinquishing the control right of that operation to the first sequencer circuit. The respective circuits in the peripheral unit can be deactivated any time as needed in accordance with the state of the data transfer operation, which is performed between the host computer system and the peripheral unit.

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patent: 5691948 (1997-11-01), Sakabe

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