Peripheral or memory device having a combined ISA bus and...

Details Peripheral or memory device having a combined ISA bus and... Peripheral or memory device having a combined ISA bus and...

2005-08-02

2005-08-02

Park, Ilwoo (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral adapting

C710S016000, C710S015000, C710S305000

Reexamination Certificate

active

06925510

ABSTRACT:
A peripheral or memory device has a bus, a first bus decoder circuit coupled to the bus for decoding a first type of bus signal, and a second bus decoder circuit coupled to the bus for decoding a second type of bus signal. The device also includes a circuit for detecting whether the bus is a first type of bus or a second type of bus, and outputting a select or detect signal to a switch. The switch is coupled to the first bus decoder circuit for providing a first bus enable signal thereto, and the switch is coupled to the second bus decoder circuit for providing a second bus enable signal thereto, depending on the nature of the select or detect signal.

REFERENCES:
patent: 5596562 (1997-01-01), Chen
patent: 5671355 (1997-09-01), Collins
patent: 5832244 (1998-11-01), Jolley et al.
patent: 5991841 (1999-11-01), Gafken et al.
patent: 6131127 (2000-10-01), Gafken et al.
patent: 6170027 (2001-01-01), Lu et al.
patent: 6286097 (2001-09-01), Chang et al.

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