Peripheral component interconnect bus test system and method...

Details Peripheral component interconnect bus test system and method... Peripheral component interconnect bus test system and method...

2007-02-21

2009-08-25

Duncan, Marc (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C702S070000, C702S071000, C702S190000

Reexamination Certificate

active

07581143

ABSTRACT:
A peripheral component interconnect (PCI) bus test system and method therefor, that is applied in a PCI test card. The PCI test card includes a static random-access-memory (SRAM). In the method, the data transaction of the PCI bus signal is disintegrated into a separate data operation, while eliminating the waveform interfering transaction. Through comparing the waveform of the data operation as separated from a PCI bus signal with the standard PCI bus waveform, the quality of the PCI bus signals can be precisely analyzed, thus realizing the hardware test of PCI bus.

REFERENCES:
patent: 4034340 (1977-07-01), Sant'Agostino
patent: 7275004 (2007-09-01), Casper et al.
patent: 2003/0051194 (2003-03-01), Cabezas et al.
patent: 2006/0168483 (2006-07-01), Sherlock et al.
patent: 2008/0005622 (2008-01-01), Takahashi et al.
patent: 2009/0055111 (2009-02-01), Williams et al.

Affiliated with

Also associated with

Rating

Peripheral component interconnect bus test system and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Peripheral component interconnect bus test system and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Peripheral component interconnect bus test system and method... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4065359