Peripheral component interconnect arbiter implementation...

Details Peripheral component interconnect arbiter implementation... Peripheral component interconnect arbiter implementation...

2007-06-19

2007-06-19

Rinehart, Mark H. (Department: 2111)

Electrical computers and digital data processing systems: input/

Access arbitrating

Access prioritizing

C710S241000, C710S242000, C710S243000

Reexamination Certificate

active

10963061

ABSTRACT:
A dynamic priority scheme is provided that uses information including the status of the target and data availability in deciding which PCI master should be assigned ownership of the bus. The target uses delayed transactions to complete a read access targeted to it. The target also integrates a buffer management scheme, in one embodiment an input/output cache, for buffer management. The present invention optimizes the performance and utilization of the PCI bus.

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