Performing multiple Reed-Solomon (RS) software error...

Details Performing multiple Reed-Solomon (RS) software error... Performing multiple Reed-Solomon (RS) software error...

2006-04-27

2009-10-06

Lamarre, Guy J (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S756000, C714S757000, C714S769000

Reexamination Certificate

active

07600176

ABSTRACT:
Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. A means is presented by which multiple Galois field computations are performed in parallel with one another. Processor, memory, and plurality of adders and/or multipliers are implemented appropriately to allow parallel Galois field computations to be performed. Multiplexing can be performed to govern the writing of resultants (generated using the adders and/or multipliers) back to the memory via feedback paths. This approach allows for parallel (as opposed to serial) implementation of the software ECC corrections with minimal area and power impact. In other words, very little space is required to implement this approach is hardware with nominal increase in power consumption, and this slight increase in power consumption provides a significant increase in ECC correction capability using this approach.

REFERENCES:
patent: 5715262 (1998-02-01), Gupta
patent: 5912905 (1999-06-01), Sakai et al.
patent: 6370671 (2002-04-01), Pan et al.

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