Performing die-to-wafer stacking by filling gaps between dies

Details Performing die-to-wafer stacking by filling gaps between dies Performing die-to-wafer stacking by filling gaps between dies

2011-05-31

2011-05-31

Huynh, Andy (Department: 2829)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S108000, C257SE21001

Reexamination Certificate

active

07951647

ABSTRACT:
An integrated circuit structure includes a bottom semiconductor chip; a top die bonded onto the bottom semiconductor chip; a protecting material encircling the bottom die and on the bottom semiconductor chip; and a planar dielectric layer over the top die and the protecting material. The protecting material has a top surface leveled with a top surface of the top die.

REFERENCES:
patent: 7098544 (2006-08-01), Edelstein et al.
patent: 7154185 (2006-12-01), Lee et al.
patent: 2005/0112795 (2005-05-01), Lee et al.
patent: 2005/0145994 (2005-07-01), Edelstein et al.
patent: 2007/0044296 (2007-03-01), Jeon et al.
patent: 2008/0012148 (2008-01-01), Takahashi
patent: 1627490 (2005-06-01), None
patent: 1926681 (2007-03-01), None
Klumpp, A., et al., “3D System Integration,” VLSI Technology, Systems and Applications, Apr. 23-25, 2007, 2 pages, IEEE.

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