Performing a memory access cycle in a multi-processor computer s

Details Performing a memory access cycle in a multi-processor computer s Performing a memory access cycle in a multi-processor computer s

1998-04-29

2000-10-31

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

711146, 711151, 711119, G06F 1200

Patent

active

061417351

ABSTRACT:
In a method and system for performing a memory access cycle from a first processor to a memory address in a multi-processor system, the memory access cycle is initiated, and, prior to completion of the memory access cycle, a snoop routine is initiated with respect to the memory address. The memory access cycle is continued without awaiting responses from another one of the processors if a second one of the processors provides a signal which indicates that immediate completion of the memory access cycle will not disturb the integrity of data stored in the system.

REFERENCES:
patent: 5265235 (1993-11-01), Sindhu et al.
patent: 5353415 (1994-10-01), Wolford et al.
patent: 5404489 (1995-04-01), Woods et al.
patent: 5426765 (1995-06-01), Stevens et al.
patent: 5463753 (1995-10-01), Fry et al.
patent: 5511226 (1996-04-01), Zilka
patent: 5524212 (1996-06-01), Somani et al.
patent: 5526510 (1996-06-01), Akkary et al.
patent: 5530932 (1996-06-01), Carmean et al.
patent: 5551005 (1996-08-01), Sarangdhar et al.
patent: 5553310 (1996-09-01), Taylor et al.
patent: 5590310 (1996-12-01), Willenz et al.
patent: 5623632 (1997-04-01), Liu et al.
patent: 5652859 (1997-07-01), Mulla et al.
patent: 5659710 (1997-08-01), Sherman et al.
patent: 5680572 (1997-10-01), Akkary et al.
patent: 5704058 (1997-12-01), Derrick et al.
patent: 5715428 (1998-02-01), Wang et al.
patent: 5717898 (1998-02-01), Kagan et al.
patent: 5740400 (1998-04-01), Bowles
patent: 5748938 (1998-05-01), Kahle
patent: 5751996 (1998-05-01), Glew et al.
patent: 5752265 (1998-05-01), Elkhoury et al.
patent: 5809534 (1998-09-01), Elkhoury
patent: 5809537 (1998-09-01), Itskin et al.
patent: 5813036 (1998-09-01), Ghosh et al.
Pentium.RTM. Pro Family Developer's Manual; vol. 1: Specifications, Chapter 7 "Cache Protocol", pp. 7-1 to 7-3; 1996.
Pentium.RTM. Pro Family Developer's Manual; vol. 3: Operating System Writer'sGuide; Chapter 11 "Memory Cache Control", pp. 11-1 to 11-5; 1996.

Affiliated with

Also associated with

Rating

Performing a memory access cycle in a multi-processor computer s does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Performing a memory access cycle in a multi-processor computer s, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Performing a memory access cycle in a multi-processor computer s will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2065273