Performing a constrained optimization to determine circuit...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000, C716S030000, C716S030000, C703S002000

Reexamination Certificate

active

11111655

ABSTRACT:
One embodiment of the present invention provides a system which performs a constrained optimization of circuit parameters. During operation, the system selects two circuit parameters associated with a circuit path, wherein the optimization is to be performed on the first circuit parameter while a limitation on second circuit parameter functions as a constraint on the optimization of the first circuit parameter. Next, the system generates objective functions which model the first circuit parameter and the second circuit parameter in terms of logical effort. The system then uses the objective functions to generate a constraint expression, wherein the constraint expression mathematically relates the optimization of the first circuit parameter to the constraint on the second circuit parameter. Next, the system computes a trade-off curve using the constraint expression. The system then computes transistor sizes for the circuit path based on a selected point from the trade-off curve.

REFERENCES:
patent: 5999714 (1999-12-01), Conn et al.
patent: 6321362 (2001-11-01), Conn et al.
patent: 6327581 (2001-12-01), Platt
patent: 6404380 (2002-06-01), Poore
patent: 6721924 (2004-04-01), Patra et al.
patent: 2004/0148579 (2004-07-01), Visweswariah
patent: 2005/0137959 (2005-06-01), Yan et al.
patent: 2006/0075365 (2006-04-01), Hershenson et al.
Conn et al., “JiffyTune: circuit optimization using time-domain sensitivities”; Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on; vol. 17, Issue 12, Dec. 1998 pp. 1292-1309.
I-Min Liu et al., “An efficient buffer insertion algorithm for large networks based on Lagrangian relaxation”, Oct. 10-13, 1999 Computer Design, 1999. (ICCD '99) International Conference on, pp. 210-215.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Performing a constrained optimization to determine circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Performing a constrained optimization to determine circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Performing a constrained optimization to determine circuit... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3959067

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.