Performance optimizing compiler for building a compiled DRAM

Details Performance optimizing compiler for building a compiled DRAM Performance optimizing compiler for building a compiled DRAM

2007-12-04

2007-12-04

An, Meng-al T. (Department: 2193)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S170000, C716S030000, C716S030000

Reexamination Certificate

active

09793037

ABSTRACT:
A compiler is provided for compiling at least one array or bank unit of a DRAM macro such that electrical performance, including cycle time, access time, setup time, among other properties, is optimized. The compiler compiles the DRAM macro according to inputted information. The compiler receives an input capacity and configuration for the DRAM macro. A compiler algorithm determines a number of wordlines and bitlines required to create the DRAM macro of the input capacity. The compiler algorithm optimizes the cycle time and access time of the DRAM macro by properly configuring a support unit of the DRAM macro based upon the number of wordlines and bitlines.

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