Performance optimization and system bus duty cycle reduction by

Details Performance optimization and system bus duty cycle reduction by Performance optimization and system bus duty cycle reduction by

1996-11-12

2000-10-03

Peikari, B. James

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711146, 711133, 711141, 711124, 711159, 711119, 711120, 711121, G06F 1212

Patent

active

061287113

ABSTRACT:
A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity which minimizing the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.

REFERENCES:
patent: 4622631 (1986-11-01), Frank et al.
patent: 5072369 (1991-12-01), Theus et al.
patent: 5155831 (1992-10-01), Emma et al.
patent: 5185861 (1993-02-01), Valencia
patent: 5265235 (1993-11-01), Sindhu et al.
patent: 5276851 (1994-01-01), Thacker et al.
patent: 5325503 (1994-06-01), Stevens et al.
patent: 5335335 (1994-08-01), Jackson et al.
patent: 5428761 (1995-06-01), Herlihy et al.
patent: 5511226 (1996-04-01), Zilka
patent: 5515514 (1996-05-01), Dhuey et al.
patent: 5526512 (1996-06-01), Arimilli et al.
patent: 5561799 (1996-10-01), Jackson et al.
patent: 5572702 (1996-11-01), Sarangdhar et al.
patent: 5572703 (1996-11-01), MacWilliams et al.
patent: 5623633 (1997-04-01), Zeller et al.
patent: 5630095 (1997-05-01), Snyder
patent: 5651137 (1997-07-01), MacWilliams et al.
patent: 5652859 (1997-07-01), Mulla et al.
patent: 5659709 (1997-08-01), Quach
patent: 5737758 (1998-04-01), Merchant
patent: 5737759 (1998-04-01), Merchant

Affiliated with

Also associated with

Rating

Performance optimization and system bus duty cycle reduction by does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Performance optimization and system bus duty cycle reduction by , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Performance optimization and system bus duty cycle reduction by will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-205549