Performance of integrated circuit components via a multiple...

Details Performance of integrated circuit components via a multiple... Performance of integrated circuit components via a multiple...

2002-07-09

2004-10-19

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C430S005000, C430S013000, C430S014000, C430S015000

Reexamination Certificate

active

06807662

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to an integrated device design. More particularly, the invention relates to a multiple exposure technique that can be used in an integrated device design and manufacturing process.
BACKGROUND OF THE INVENTION
In the semiconductor industry, integrated circuit (IC) devices are fabricated by forming several device layers on a semiconductor substrate using lithographic methods to define the pattern of each layer. As integrated circuits (ICs) become more dense, the widths of lines and components become increasingly smaller. Shrinkage of IC device dimensions can make it difficult to print patterns by a single exposure. This difficulty usually arises with such features of IC devices as transistor gates that have especially small dimensions. In addition, transistor gates are laid out randomly across the device and are not surrounded sufficiently close by other features to provide the necessary periodicity for maximum resolution. One solution to resolution enhancement on the gate layer is the adoption of a multiple exposure technique.
Existing multiple exposure techniques utilize expensive phase-shifting masks (PSMs). For example, a common multiple-exposure technique uses an alternating PSM to print the desired feature and a trim mask to remove the residual image produced by the alternating PSM. Alternating PSMs are expensive because their fabrication requires additional steps for creating the 180-degree phase difference and also due to enhanced printing of small defects that are difficult to detect and repair. Accordingly, the cost associated with alternating PSMs may outweigh the benefit received from the double exposure fabrication process in terms of chip speed and performance. Thus, what is needed is an improved multiple-exposure technique that utilizes low-cost reticles.
SUMMARY OF THE INVENTION
An initial layout of an integrated circuit device is separated into a set of definitions for use in a multiple exposure fabrication process. The separation begins with reading a portion of the initial layout and identifying one or more target features within the initial layout. Further, a first revised layout definition is created for a first mask and a second revised layout definition is created for a second mask. The first revised layout definition includes the target features inside the dark-field content. In addition, in one embodiment, the first revised layout definition includes clear areas around each target feature. The second layout definition includes one or more dark features inside the bright-field content. These dark features, when used in the multiple exposure fabrication process, will overlap the target features. The first and second masks may be binary masks, attenuated phase-shifting masks (PSMs) or a combination of a binary mask and an attenuated PSM.
Other features of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.


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