Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
1998-10-30
2001-11-06
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S052000, C709S236000, C370S394000
Reexamination Certificate
active
06314477
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the reception of Fibre Channel frames by a Fibre Channel port, and, in particular, to a hardware implementation of an interface controller within a Fibre Channel port for quickly and efficiently locating the position in host memory into which to place the data contained in each received Fibre Channel frame.
BACKGROUND OF THE INVENTION
The Fibre Channel (“FC”) is an architecture and protocol for a data communication network that interconnects a number of different combinations of computers and peripheral devices. The FC supports a variety of upper-level protocols, including the small computer systems interface (“SCSI”) protocol. A computer or peripheral device is linked to the network through an FC Port and copper wires or optical fibers. An FC Port includes a transceiver and an interface controller, and the computer peripheral device in which the FC Port is contained is called a “host.” The FC Port exchanges data with the host via a local data bus, such as a peripheral computer interface (“PCI”) bus. The interface controller conducts lower-level protocol exchanges between the Fibre Channel and the computer or peripheral device in which the FC Port resides.
A high-level Fibre Channel transaction involves the exchange between FC Ports of one or more FC sequences. An FC sequence is, in turn, composed of one or more sequentially ordered FC frames. As an FC Port receives the FC frames comprising an FC data sequence, the FC Port extracts the data from each FC frame and places the data into host memory. The host memory into which the data is placed may be composed of one or more host memory buffers. These host memory buffers may not be contiguous in memory. However, the data received for an FC data sequence must be organized within these memory buffers sequentially, starting from the first byte of the first data frame of the sequence and proceeding to the final byte of the final data frame of the sequence. The header of each FC data frame contains a relative offset field that indicates the relative offset of the data contained in that data frame from within the entire FC data sequence in which the data frame is contained. Upon receipt of an FC data frame, an FC Port must either be able to quickly calculate where to place the data contained in that data frame into one or more memory buffers via one or more direct memory access (“DMA”) operations, or must instead pass the received data and relative offset of the received data to the host so that the host can make the calculations and move the data into the data buffers. The latter alternative incurs redundant data copying and is impracticably slow and host processor-intensive in the high-band width and high-speed Fibre Channel communications network.
Currently available and previously available FC Ports achieved the required efficiency and speed in reassembling received data into host memory buffers by placing restrictions on the size and alignment of the host memory buffers, or by requiring that all FC data frames of an FC data sequence be received in order. In certain FC topologies, in-order data frame reception is more or less guaranteed; however, in other FC topologies in-order FC frame reception is not guaranteed. Furthermore, it is difficult, under many computer operating systems, for a host computer to acquire correctly aligned memory buffer of specific sizes. Thus, the restrictions required by currently available and previously available FC Ports for reassembling FC data sequence data in host memory make it impractical or impossible for FC Ports to function in many environments. A need has therefore been recognized by FC Port designers and manufacturers for a method to implement, in hardware within an FC Port, quick and efficient reassembling of FC data sequence data, some of which may be received out of order, into byte-aligned host memory buffers of arbitrary sizes.
SUMMARY OF THE INVENTION
The present invention provides a Fibre Channel (“FC”) interface controller that implements, in hardware, an efficient method for reassembling the data contained in FC data frames into arbitrarily-sized and byte-aligned host memory buffers. The host computer allocates and initializes a transaction status block (“TSB”) to contain various information required by an FC Port to carry out a Fibre Channel protocol (“FCP”) transaction. The TSB may contain the length and addresses of three host memory buffers, or may contain a pointer to auxiliary data structures that contain a number of length and address pairs describing host memory buffers. The TSB is initialized by the host to contain information about the next expected FC data frame and the location in the host memory buffers into which the FC Port needs to place the data contained in the next expected FC data frame. If a data frame is received by an FC Port out of order with respect to the FC data sequence in which the FC data frame is contained, the FC Port can nonetheless determine a position within the host memory buffers to place the data contained in that data frame. The FC port subsequently and automatically maintains the information about the next expected FC data frame.
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Cowger Bryan J
Mathew Brandon H
Steinmetz Joseph H
Wakeley Matthew P
Agilent Technologie,s Inc.
Elamin Abdelmoniem
Lee Thomas
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