Performance in flash memory devices

Details Performance in flash memory devices Performance in flash memory devices

2003-02-05

2004-04-20

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S257000

Reexamination Certificate

active

06723638

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates generally to semiconductor devices, and more particularly, to improved performance of flash memory devices.
2. Background Art
A type of programmable memory cell is commonly referred to as a flash memory cell. Such flash memory cell may include a source and a drain formed in a silicon substrate, or in a well that is formed in the silicon substrate. The flash memory cell includes a stacked gate structure formed on the silicon substrate. The region of the silicon substrate beneath the stacked gate structure is known as the channel region of the flash memory cell.
The stacked gate structure of the flash memory cell includes a pair of polysilicon structures separated by oxide layers. One of the polysilicon structures functions as a floating gate and the other polysilicon structure functions as a control gate for the flash memory cell. The oxide layer that separates the floating gate from the silicon substrate is commonly referred to as a tunnel oxide layer, A memory cell of this type is shown and described in U.S. Pat. No. 4,698,787, “Single Transistor Electrically Programmable Memory Device and Method”, issued to Mukherjee et al. on Oct. 6, 1987.
Programming operations on a flash memory cell involve the application of a relatively large constant voltage to the drain of the flash memory cell while an even larger voltage is applied to the control gate. During such a programming operation, the source of the flash memory cell is maintained at a ground level or a zero voltage level in relation to the voltages applied to the control gate and drain. The high constant voltage applied to the control gate raises the voltage potential of the floating gate to a high level at the start of the programming operation. Such a high voltage potential on the floating gate attracts the electrons floating through the channel region. Under these conditions, electrons in the channel region having sufficiently high kinetic energy inject through the tunnel oxide layer and onto the floating gate. This phenomenon is commonly referred to as hot carrier programming or hot carrier injection. A successful programming operation involves the injection of sufficient numbers of electrons onto the floating gate to achieve a desired threshold voltage for the flash memory cell. The threshold voltage is the voltage that must be applied to the control gate of the flash memory cell to cause conduction through the channel region during the read operation on the flash memory cell.
In a typical memory array which includes a large number of cells, a cell can be programmed by applying programming voltages of approximately 9-10 volts to the control gate, approximately 5 volts to the drain, and grounding the source. These voltages cause hot electrons to be injected from a drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein that increases the threshold of the cell to a value in excess of approximately 4 volts.
A cell can be read by applying a voltage of approximately 5 volts to the control gate, applying approximately 1 volt to the bit line to which the drain is connected, grounding the source, and sensing the bit line current. If the cell is programmed and the threshold voltage is relatively high (5 volts), the bit line current will be zero or relatively low. If the cell is not programmed or is erased, the threshold voltage will be relatively low (2 volts), the control gate voltage will enhance the channel, and the bit line current will be relatively high.
A cell can be erased in several ways. In one approach, applying a relatively high voltage, typically 12 volts, to the source, grounding the control gate and allowing the drain to float erases a cell. This causes the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Applying a negative voltage on the order of −10 volts to the control gate, applying 5 volts to the source and allowing the drain to float can also erase the cell. Another method of erasing a cell is by applying 5 volts to the P well and −10 volts to the control gate while allowing the source and drain to float.
FIGS. 1 and 2
illustrate the formation of a typical stacked gate structure in accord with the prior art. As shown therein, the silicon dioxide layer
10
that will form the tunnel oxide is thermally grown on a silicon substrate
12
. Then, a polysilicon layer
14
is provided on the oxide layer
10
, a dielectric layer
16
, for example, an ONO layer is provided on the polysilicon layer
14
, and another polysilicon layer
18
is provided on the dielectric layer
16
. A layer of photoresist is provided on the polysilicon layer
18
and is patterned as shown in
FIG. 1
, leaving photoresist layer portion
20
on the polysilicon layer
18
. Then, an etch step is undertaken, using the photoresist layer portion
20
as a mask (FIG.
2
), to etch through the polysilicon layer
18
, dielectric layer
16
, polysilicon layer
14
and oxide layer
10
, down to the substrate
12
, forming the gate stack
22
which includes tunnel oxide
10
A, polysilicon floating gate
14
A, dielectric
16
A, and polysilicon word line
18
A. The photoresist layer portion
20
is then removed.
As is well-known, the etch step used to form the gate stack
22
can cause gouging of the silicon substrate
12
adjacent the gate oxide
10
A (see arrows A and B, FIG.
2
), which, if allowed to remain in that state, can result in severely degrading erase integrity and erase distribution of the device. In order to reduce this problem, typically, a layer of pre-implant thermal oxide
24
is grown on the top and sides of the gates stack
22
and on the exposed portions of the silicon substrate
12
(FIG.
3
), for example to a thickness of 100 angstroms, which substantially reduces or repairs the damage in the substrate
12
described above. Then, ion implantation
26
is undertaken (FIG.
4
), using the gate stack
22
and the portions
24
A,
24
B of the oxide layer
24
on the sides of the gate stack
22
as a mask, to implant the source and drain regions
28
,
30
of the device.
Typically, growth of the pre-implant oxide
24
is undertaken for a substantial length of time, for example, five minutes, to a thickness of for example 100 angstroms. Growing the oxide
24
for this length of time has been found to substantially degrade charge carrier mobility in the channel region of the device. This results in a significant core gain drop or drive current drop in the device, clearly a negative effect on device performance. In addition, this lengthy oxidation step has been found to cause oxide regions
32
,
34
to be grown into the sides of the floating gate
14
A near the bottom thereof (at the sides of the gate stack
22
, see FIGS.
3
and
4
). These undesired oxide regions
32
,
34
can cause significant problems in erase speed of the device.
Therefore, what is needed is an approach which overcomes these problems by providing a pre-implant oxide layer which repairs damage in the substrate caused by the gate stack etch, meanwhile avoiding the problems recited above associated with growing this oxide layer for a substantial period of time.
DISCLOSURE OF THE INVENTION
In the present method of fabricating a semiconductor device, a gate oxide layer is provided on a silicon substrate. A first polysilicon layer is provided on the gate oxide layer, a dielectric layer is provided on the first polysilicon layer, and a second polysilicon layer is provided on the dielectric layer. Upon appropriate masking, and etch step is undertaking, etching the second polysilicon layer, dielectric layer, first polysilicon layer, and gate oxide layer to remove portions thereof to expose the silicon substrate and to form a stacked gate structure on the silicon substrate. A rapid thermal anneal is undertaken for a short period of ti

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