Performance enhancing memory interleaver for data frame processi

Details Performance enhancing memory interleaver for data frame processi Performance enhancing memory interleaver for data frame processi

1996-06-13

1998-07-07

Swann, Tod R.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

711 3, 711101, 711118, 711202, 711205, 711206, G06F 1202

Patent

active

057784140

ABSTRACT:
Disclosed is a frame processing engine for receiving and processing a data frame having a header and a payload, comprising a first memory for receiving at least a portion of the header of the data frame; a second memory for receiving the payload of the data frame; and a controller, upon receipt of the data frame, for storing the header (at least most of it) in the first memory and the remainder of the data frame (including the payload) in the second memory, with the first memory having a shorter access time than the second memory.

REFERENCES:
patent: 5398245 (1995-03-01), Harriman, Jr.
W. Stallings, Computer Organization and Architecture, 4th Ed., pp. 121-147.

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