Perforated plasma confinement ring in plasma reactors

Details Perforated plasma confinement ring in plasma reactors Perforated plasma confinement ring in plasma reactors

2000-11-30

2003-01-14

Mills, Gregory (Department: 1763)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C427S569000, C216S067000, C156S345470, C118S7230ER

Reexamination Certificate

active

06506685

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the fabrication of semiconductor integrated circuits (IC's). More particularly, the present invention relates to an improved apparatus and method for etching through a silicon-dioxide containing material, during IC fabrication to create etched features (e.g., trenches, contacts or vias) on the substrate surface.
During the manufacture of a semiconductor-based product, for example, a flat panel display or an integrated circuit, multiple deposition and/or etching steps may be employed. During the deposition step, materials are deposited onto a substrate surface (such as the surface of a glass panel or a wafer). Conversely, etching may be employed to selectively remove materials from predefined areas on the substrate surface. Etching in this manner can create etched features in the dielectric layers of a substrate,surface wherein the etched features are filled with metal to form a conductive path.
During etching, a mask formed of a suitable mask material, such as photoresist, is typically employed to define the areas to be etched in the underlying layer. In an exemplary photoresist technique, the photoresist material is first deposited on the underlying layer to be etched. The photoresist material is then patterned by exposing the photoresist material in a suitable lithography system, and by developing the photoresist material to form a mask to facilitate subsequent etching. Using an appropriate etchant, areas of the underlying layer that are unprotected by the mask may then be etched away using an appropriate etchant source gas, thereby forming etched features such as trenches, contacts or vias in the underlying layer.
To facilitate discussion,
FIG. 1
depicts an exemplary substrate stack
10
, including a mask
12
, an underlying layer
14
and a substrate
16
. As mentioned, mask
12
may represent photoresist mask or it may be formed of any suitable mask material, including hard mask materials. Underlying layer
14
represents the layer or layers to be etched. For ease of discussion, the underlying layer represents herein a dielectric layer (e.g., a doped or undoped silicon dioxide-containing layer) although, depending on the specific application, the underlying layer may be formed of any etchable material including, for example, organic material. Substrate
16
includes the layers and features that underlie the layer to be etched and may include the semiconductor wafer or the glass panel itself. For the purposes of the invention herein, the composition substrate
16
is somewhat irrelevant.
Within mask
12
, there is shown an opening
18
, which is created during the mask patterning process. Through opening
18
, plasma generated etchants react with the material of underlying layer
14
to etch features (e.g., trenches, contacts or vias) in the underlying layer. During this etching process, the etchants tend to anisotropically etch underlying layer
14
through opening
18
in mask
12
, forming an etched feature
20
(e.g., trenches, contacts or vias) having a diameter
22
(or width) and a depth
24
. The diameter (or width) is the feature size. The aspect ratio is the ratio of depth over the feature size.
To achieve greater circuit density, modern integrated circuits are scaled with increasingly narrower design rules. As a result, the need for high aspect ratios for features (e.g., trenches, contacts or vias) and substantially straight profiles between devices on the integrated circuit has steadily increased. By way of example, it is not uncommon to employ design rules as small as 0.18 microns or even smaller in the fabrication of some high density integrated circuits. As adjacent devices are packed more closely together, the need for high aspect ratios and straight profiles are increased. The higher aspect ratios allow the feature size (diameter or width) to be smaller thereby allowing closer packing. Additionally, straight profiles ensure that subsequently deposited metal material can properly fill the etched feature, e.g., without suffering voids due to pinch-offs, or the like.
In view of the foregoing, these are desired: improved methods and apparatuses for etching features with high aspect ratios and more vertically etched profiles.
SUMMARY OF THE INVENTION
The invention relates, in one embodiment, to a plasma processing reactor apparatus for semiconductor processing a substrate. The apparatus includes a chamber. The apparatus further includes a top electrode configured to be coupled to a first RF power source having a first RF frequency and a bottom electrode configured to be coupled to second RF power source having a second RF frequency that is lower than the first RF frequency. The apparatus additionally includes an insulating shroud that lines an interior of the chamber, the insulating shroud being configured to be electrically floating during the processing. The apparatus further includes a perforated plasma confinement ring disposed outside of an outer periphery of the bottom electrode, a top surface of the perforated plasma confinement ring being disposed below a top surface of the substrate and electrically grounded during the processing.
The invention relates, in another embodiment, to a perforated plasma confinement ring device configured for grounding electrons inside a plasma processing reactor during processing. The apparatus includes a conductive ring having an inner and outer diameter, the inner diameter being dimensioned to surround an electrode in the plasma processing reactor, the conductive ring being electrically grounded during the processing. The apparatus further includes a plurality of perforations in the conductive ring, the plurality of perforations being dimensioned to permit by-product gases from the processing to pass through while substantially confining a plasma.
The invention relates, in yet another embodiment, to a method of etching a substrate in semiconductor processing. The method includes providing a plasma processing reactor that includes a process chamber, a top electrode coupled to a first RF power source, a bottom electrode coupled to a second RF power source, a perforated plasma confinement ring coupled to ground, an insulating shroud, a process gas and a substrate. The method further includes filling the process chamber with the process gas and energizing the process gas with the top electrode such that a plasma is formed inside the process chamber. The method additionally includes grounding the plasma with the perforated plasma confinement ring and removing by-product gases the processing through a plurality of perforations in the perforated plasma confinement ring.
These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.


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