Percent-of-clock delay circuits with enhanced phase jitter...

Details Percent-of-clock delay circuits with enhanced phase jitter... Percent-of-clock delay circuits with enhanced phase jitter...

2005-09-20

2005-09-20

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C375S376000

Reexamination Certificate

active

06946888

ABSTRACT:
DLL integrated circuits include least one delay element associated with the generation of an internal clock signal and a control circuit that is configured to periodically adjust a delay of said at least one delay element in response to a first clock signal (CLK). The control circuit is further configured to block at least one periodic adjustment of the delay of the at least one delay element in response to detecting excessive jitter with CLK. This DLL may be configured to block at least one periodic adjustment to a phase of an internal clock signal (ICLK) in response to detecting an excessive phase difference between the first clock signal (CLK) and a feedback clock signal (FCLK) derived from the internal clock signal (ICLK).

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