Per cache line semaphore for cache access arbitration

Details Per cache line semaphore for cache access arbitration Per cache line semaphore for cache access arbitration

2005-08-09

2005-08-09

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S151000, C711S152000, C711S168000, C711S145000

Reexamination Certificate

active

06928525

ABSTRACT:
A semaphore mechanism in a multiport cache memory system allows concurrent accesses to the cache memory. When there is no contention for the same cache line, multiple requesters may access the cache memory concurrently. A status bit in each cache line indicates whether that particular cache line is in use, and is used to arbitrate among various requesters for the same cache line. When at least two requests for the same cache line is received, a cache arbiter examines the status bit to determine if the requested cache line is in use. If the cache line is not already in use, the cache arbiter selects, and sends a signal granting the request to, the requesters one at a time to allow access to the contested cache line, while allowing concurrent access to the cache memory to other requesters requesting different cache lines. The semaphore mechanism allows exchanges of signals between the cache arbiter and the requesters to provide an orderly arbitration of multiple requests for the same cache line.

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