Peeling free metal silicide films using rapid thermal anneal

Details Peeling free metal silicide films using rapid thermal anneal Peeling free metal silicide films using rapid thermal anneal

1992-08-10

1995-02-28

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437200, 437247, H01L 21265

Patent

active

053936850

ABSTRACT:
A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which provides a peeling-free metal silicide gate electrode devices. The process uses annealing of the gate oxide, the polysilicon layer and the metal silicide layer using a rapid thermal annealing process at a temperature more than about 1000.degree. C. and for a time of between about 30 to 60 seconds. A pattern of lightly doped regions is formed in the substrate by ion implantation using the structures as the mask. A low temperature silicon dioxide layer is blanket deposited over the surfaces of the structure. The blanket layer is etched to form a dielectric spacer structure upon the sidewalls of each of the gate electrode structures and over the adjacent portions of the substrate, and to remove the silicon oxide layer from the top surfaces of metal silicide layer. Driving in the pattern of lightly doped regions is accomplished by rapid thermal annealing at a temperature of more than about 1000.degree. C. and for a time of between about 30 to 60 seconds with the metal silicide layer having no covering thereover. Heavily doped regions are now formed in the substrate to produce the lightly doped drain under the spacer structure of an MOS FET device. A passivation layer is formed over the structures and electrical connecting structures thereover.

REFERENCES:
patent: 4690730 (1987-09-01), Tang et al.
patent: 4808544 (1989-02-01), Matsui
patent: 5015595 (1991-05-01), Wollesen
patent: 5089432 (1992-02-01), Yoo
patent: 5168072 (1992-12-01), Moslehi
patent: 5206187 (1993-04-01), Doan et al.

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