Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-04-26
2002-09-24
Crane, Sara (Department: 2911)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S536000, C257S537000, C257S752000, C257S762000
Reexamination Certificate
active
06455914
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit (IC) chips which can be tailored to include a fuse. The invention further relates to a method of making the improved circuit.
2. Related Art
Laser deletion of thick metal fuses is difficult due to the mass of metal that must be removed without damage to surrounding and underlying structures.
In the manufacture of semiconductor integrated circuits, wiring layers are deposited and defined and interconnected with conductive vias through a series of well known photolithography and metal etching steps. Each such wiring level is coated with a layer of a glassy protective material, known as a passivation layer, which protects and insulates the wiring of each layer. The creation of integrated circuits with such multiple wiring layers is well known to the semiconductor art.
In some circuits, such as CMOS logic circuits, the fuses designed in the circuit are often formed in regular arrays in the upper most layers of wiring and in a position such that other wiring is not placed immediately over or under the fuses. In such arrays the fuses are often aligned in parallel rows and placed as closely together as is possible. By opening selected ones of these fuses the logic elements of the circuits can be arranged in different combinations to perform different logic functions or correct manufacturing defects.
These fuses are typically opened by applying a laser pulse of sufficient size, duration and power as to superheat and vaporize the metal forming the fuse. This superheating of the fuse and its vaporization fractures and blows away a portion of the overlying glassy protective layer creating a saucer shaped crater in the protective layer. When the protective layer ruptures, cracks can radiate outwardly causing additional damage such as breakage of, or the uncovering of, adjacent fuse elements. Such uncovering of the adjacent elements can cause subsequent corrosion and premature failure of the circuit. While fuses are typically opened using a laser, they may also be opened by passage of electrical current or exposure to an ion beam which ablates (or removes or sputters) away the fuse link. The described invention is also useful for these methods of fusing.
The reader is referred to the following patents related to fuses including “Array Protection Devices and Fabrication Method,” U.S. Pat. No. 5,523,253, and “Array Fuse Damage Protection Devices and Fabrication Method,” U.S. Pat. No. 5,420,455, both to Richard A. Gilmour, et al. and of common assignee to this invention, the contents of which are incorporated herein by reference in their entireties.
Fuses are used in semiconductor chips to provide redundancy, electrical chip identification and customization of function. For designs having three (or more) layers of wiring, the fuses are typically formed from a segment of one of the wiring layers, e.g., the “last metal” (LM) or “last metal minus one” (LM-1) wiring layer. Fusing, i.e., the deletion of a segment of metal fuse line, is accomplished by exposing the segment of metal fuse line to a short, high intensity pulse of “light” from an infra-red (IR) laser. The metal line absorbs energy, melts and expands, and ruptures any overlain passivation. The molten metal then boils or vaporizes out of its oxide surroundings, disrupting line continuity and causing high electrical resistance. A “sensing” circuit is used to detect fuse segment resistance.
Laser deletion of thick metal fuses is difficult due to the mass of metal that must be removed without damage to surrounding structures. As the mass of the fuse link increases or the melting temperature of the fuse link metal increases, higher laser energies and longer (or multiple) laser pulses are required to accomplish deletion. Higher energies and longer pulses provide sufficient energy to adjacent and underlying structures, e.g., silicon under the fuse area, to cause severe damage to the interlayer dielectric (ILD) oxide and adjacent fuse wiring. What is needed is a way to eliminate the need to use high laser energies.
SUMMARY OF THE INVENTION
The present invention includes a method for forming a thin pedestal fuse segment in a thick last metal (LM) wiring line, including the steps of forming a last metal minus 1 (LM-1) wiring layer and an overlaying oxide inter layer dielectric (ILD) using conventional techniques, depositing a layer of nitride using conventional techniques, wherein a thickness of the nitride layer is an approximate thickness desired for the thin pedestal fuse segment, defining with a resist layer and mask the LM wiring line that will contain a fuse link, wherein the fuse link is not yet imaged, etching the nitride layer and the oxide ILD, forming a thick line trench, stripping the resist, applying a new layer of resist and opening an image, defining the fuse link overlapping adjacent ends of an interrupted LM trench, etching the nitride layer using an etchant, stripping the new layer of resist, applying another layer of resist and imaging and etching via contacts, wherein the via contacts will connect the LM to the LM-1 wiring layers, stripping the another layer of resist, filling the wiring trench with at least one metal, and polishing to remove unwanted and excess metal, forming a LM damascene fuse line having the thin pedestal fuse segment.
In one embodiment of the invention, the oxide layer includes silicon dioxide. In another, the nitride layer includes silicon nitride. In yet another embodiment, the deposition steps can include chemical vapor deposition (CVD)and physical vapor deposition (PVD) techniques.
In one embodiment of the invention, the etching step includes using an etchant that is relatively selective to the nitride. In another embodiment, if the nitride layer is thin, selectivity is not required.
In another embodiment of the invention, the wiring trench can be filled with copper.
In an embodiment of the invention, the polishing step can include using at least one of a chemical and a mechanical polishing technique.
In another embodiment of the invention, a method for forming a thin pedestal fuse segment in a last metal (LM) wiring line includes the steps of forming a last metal minus 1 (LM-1) wiring layer and an overlaying oxide inter layer dielectric (ILD) layer using conventional techniques, depositing a layer of nitride using conventional techniques, wherein a thickness of the nitride layer is an approximate thickness desired for the thin pedestal fuse segment, defining with a resist layer and mask the LM wiring line that will contain a fuse link, wherein the fuse link is not yet imaged, etching the nitride layer and the underlying oxide ILD, forming a thick wiring line trench, stripping the resist layer, applying a new layer of resist and opening an image over an interrupted segment, etching selectively the oxide to form vias using an etch selective to the oxide, leaving exposed a nitride pedestal cap, etching selectively the nitride pedestal cap using an etch selective to the nitride, stripping the new layer of resist, filling the wiring line trench with at least one metal, and polishing to remove unwanted and excess metal, forming LM damascene fuse line having the thin pedestal fuse segment.
In an embodiment of the invention, the first etching step includes using an etchant that is relatively selective to the nitride.
In another embodiment, the second etching step includes using an etchant, wherein if the nitride layer is thin, selectivity is not required.
In yet another embodiment, the invention includes filling the wiring line trench with copper metal. In another embodiment, the polishing step includes using a chemical or a mechanical polishing technique.
In another embodiment of the invention, a metallization structure formed on a semiconductor substrate, includes an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper layer being thinner than the lower layer, the insulator structure having a plurality of openings therein
Bouldin Dennis P.
Daubenspeck Timothy H.
Motsiff William T.
Canale Anthony
Crane Sara
Walter, Jr. Howard J.
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