Pedestal collar structure for higher charge retention time...

Details Pedestal collar structure for higher charge retention time... Pedestal collar structure for higher charge retention time...

2000-06-22

2002-06-11

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000, C257S302000, C257S304000, C257S305000

Reexamination Certificate

active

06404000

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to DRAM memory cell structures, and in particular, a trench-type capacitor with enhanced charge retention.
2. Description of the Related Art
Traditional trench capacitors naturally discharge over time. One cause of such discharge is the leakage current between the storage node and the buried plate (i.e., surface node diffusion). One way to increase charge retention time is by reducing leakage current between the storage node diffusion and the buried plate.
Referring to FIG.
1
(
a
), an example of one major leakage pathway in a conventional trench-type memory cell is depicted using a parasitic vertical transistor
10
. The transistor
10
includes collar oxide
11
formed on the interior surface
12
of trench
13
. Transistor
10
is incorporated into DRAM memory cell
16
which further includes a gate
17
, storage nodes
13
,
18
and a buried plate
19
.
FIG.
1
(
b
) depicts an electrical circuit diagram corresponding to the transistor
10
.
Several conventional methods have been proposed or implemented to address current leakage. Increasing the threshold voltage of parasitic transistor
10
can reduce the leakage current. The threshold voltage can be increased by ion (p-type in case of p-type well) implantation into the well at a depth within the parasitic channel. Threshold voltage can also be increased by increasing the collar oxide
11
thickness.
However, both of the methods have problems when incorporated into a high density DRAM process. For example, ion implantation can induce undesirable impurities into other areas. Since the aspect ratio (collar depth/trench opening) is very high (e.g. 1 &mgr;m /0.15 &mgr;m=6.7), the implantation angle needs to be almost parallel to collar oxide or vertical to wafer surface. As a result of the implantation angle, relatively high energy ion implantation is necessary and may result in undesirable implantation into the active channel region.
A disadvantage of a thicker collar oxide is a reduction in the trench opening. Reducing the trench opening leads to an increase in storage electrode resistance. An additional disadvantage of reducing the trench opening is the possible increase in complexity required to fill a trench with a narrow opening.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for a trench-type capacitor with enhanced charge retention.
According to one aspect of the present invention, a memory structure has a trenched formed in a substrate. A collar oxide is located in an upper portion of the trench and includes a pedestal portion.
According to another aspect of the present invention, a dynamic random access memory device includes a trench formed in a substrate having an upper portion. A collar oxide is located in the upper portion of the trench. The collar oxide includes a pedestal. A conductor fills the trench. The pedestal reduces a leakage of a charge on the conductor.
According to yet another aspect, the present invention comprises a method of forming a memory device. The method includes forming a trench in a substrate. A non-conformal oxide is deposited in an upper portion of the trench, wherein the non-conformal oxide is thicker along horizontal surfaces than vertical surfaces. Pedestals are formed on a lower portion of the non-conformal oxide.


REFERENCES:
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patent: 5432365 (1995-07-01), Chin et al.
patent: 5482883 (1996-01-01), Rajeevakumar
patent: 5618751 (1997-04-01), Golden et al.
patent: 5723355 (1998-03-01), Chang et al.
patent: 5847432 (1998-12-01), Nozaki
patent: 5945704 (1999-08-01), Schrems et al.
patent: 6184549 (2001-02-01), Furukawa et al.
patent: 04304654 (1992-10-01), None
D. M. Kennedy, “Post Diffusion Insulation”, IBM Technical Disclosure Bulletin, vol. 32, No. 5B, Oct. 1989, pp. 384-385.

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