PECL input buffer

Details PECL input buffer PECL input buffer

1995-01-03

1996-10-29

Hudspeth, David R.

Electronic digital logic circuitry

Interface

Logic level shifting

326 68, 326 83, H03K 190175

Patent

active

055700420

ABSTRACT:
According to the present invention, an input buffer is utilized to first amplify a differential clock or data signal pair to a desired voltage level before being presented to a CMOS or NMOS differential amplifier. In a preferred embodiment of the present invention, a PECL input buffer is comprised of a plurality of n-channel transistors which are capable of quickly amplifying the voltage level of the differential input signal pair.

REFERENCES:
patent: 4980583 (1990-12-01), Dietz
patent: 5105107 (1992-04-01), Wilcox
patent: 5128556 (1992-07-01), Hirakata
patent: 5245228 (1993-09-01), Harter
patent: 5317214 (1994-05-01), Lewis
patent: 5343094 (1994-08-01), Nguyen
patent: 5444396 (1995-08-01), Soneda

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