Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2011-06-07
2011-06-07
Nguyen, Linh V (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S026000, C326S027000, C326S030000, C326S087000
Reexamination Certificate
active
07956644
ABSTRACT:
A semiconductor device includes a first circuit block, a second circuit block, and a data bus. The data bus is coupled between the first and second circuit blocks. A first data inverter on the data bus inverts a selected segment of data that is transferred onto the data bus. A second data inverter at an end of the data bus re-inverts the selected segment of data before the data is transferred off the data bus. The data that is transferred onto the data is not analyzed in order to determine the selected segment of data that is inverted.
REFERENCES:
patent: 5107148 (1992-04-01), Millman
patent: 5555513 (1996-09-01), Harrington et al.
patent: 5654927 (1997-08-01), Lee
patent: 5914909 (1999-06-01), Park
patent: 6242962 (2001-06-01), Nakamura
patent: 6269033 (2001-07-01), Ishida et al.
patent: 6563745 (2003-05-01), Ilkbahar
patent: 6633951 (2003-10-01), Cohen
patent: 7262637 (2007-08-01), Pan et al.
patent: 7280412 (2007-10-01), Jang et al.
patent: 7358872 (2008-04-01), Morzano et al.
patent: 7400541 (2008-07-01), Jang et al.
patent: 7403036 (2008-07-01), Bando et al.
patent: 7688102 (2010-03-01), Bae et al.
patent: 2003/0046483 (2003-03-01), Moschopoulos
Dicke Billig & Czaja, PLLC
Nguyen Linh V
Qimonda AG
LandOfFree
Peak power reduction using fixed bit inversion does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Peak power reduction using fixed bit inversion, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Peak power reduction using fixed bit inversion will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2722183