Peak error detector

Details Peak error detector Peak error detector

1998-05-12

2001-04-24

Chung, Phung M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S812000

Reexamination Certificate

active

06223325

ABSTRACT:

A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the patent and trademark office, patent file or records, but otherwise reserves all copyright rights whatsoever.
This application is submitted with a microfiche appendix containing copyrighted material, copyright 1996, National Semiconductor Corporation. Such appendix consists of 3 microfiche transparencies with a total of 293 frames.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuits for detecting errors in peak signal amplitudes of digital data signals, and in particular, to peak error detection circuits for detecting and identifying valid detected peak signal errors during selected time windows within digital data signals.
2. Description of the Related Art
Recovering data from data signals which have been transmitted over long lengths of cable at high data rates requires that such data signals be equalized in order to compensate for the signal loss and phase dispersion characteristics of the cable. Further, in those applications where the cable length may vary, such equalization must be capable of adapting according to the length of the cable. Conventional adaptive equalization is typically accomplished through the use of a feedback control signal having an amplitude which is proportional to the pulse height of the equalized data signal. However, such a technique for controlling the adaptive equalization process is very sensitive to amplitude errors in the incoming data signal. Accordingly, it would be desirable to have a peak error detector which, by detecting and identifying valid detected errors in the signal peaks of the incoming data signal, can be used to help generate more consistent and more accurate control over the adaptive equalization process.
SUMMARY OF THE INVENTION
A peak error detector in accordance with the present invention provides for the generation of multiple peak error signals indicating the occurrence of errors in the signal peaks within selected frequency bands of the incoming data signal. Such peak error signals identify errors between the peak of the present incoming data signal and estimated peak values of prior data signals within different time windows. Such a peak error detector can be used advantageously in a signal peak tracker or a baseline wander compensation circuit, as well as a control circuit for an adaptive equalizer (e.g., for use in a fast Ethernet transceiver).
A data signal peak error detector in accordance with one embodiment of the present invention includes first and second data signal detection circuits. The first data signal detection circuit is configured to receive and detect an input data signal which includes a plurality of signal levels representing an N-level data signal and in accordance therewith provide a data level signal which is asserted when the input data signal level extends beyond a predetermined value. The input data signal includes, associated therewith, a plurality of sequential intermediate signal values and a plurality of sequential extended signal values each of which extends beyond a preceding one of the plurality of sequential intermediate signal values. The predetermined value corresponds to a value which is between a preceding one of the plurality of sequential intermediate signal values and a preceding one of the plurality of sequential extended signal values. The second data signal detection circuit is configured to receive the first data level signal and in accordance therewith provide one or more signal pulses during the assertion of the first data level signal. Each one of the one or more signal pulses is provided at a respective time after the assertion of the first data level signal.
These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.


REFERENCES:
patent: 5710660 (1998-01-01), Yamamoto et al.
patent: 5850514 (1998-12-01), Gonda et al.
patent: 6044489 (2000-03-01), Hee et al.

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