PCI system controller capable of delayed transaction

Details PCI system controller capable of delayed transaction PCI system controller capable of delayed transaction

1999-11-30

2004-02-17

Thai, Xuan M. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S107000

Reexamination Certificate

active

06694400

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88106504, filed Apr. 23, 1999. The present application is related to copending filed on the same date as this application, entitled “DELAYED TRANSACTION METHOD AND DEVICE USED IN A PCI SYSTEM” by LAI et al., currently pending.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for controlling peripheral components. More particularly, the present invention relates to the transfer of data via a peripheral component interconnect (PCI) bus.
2. Description of Related Art
FIG. 1
shows a conventional computer architecture that uses a PCI bus. As shown in
FIG. 1
, a PCI host bridge
12
is coupled to a PCI bus
14
. The PCI bus
14
is capable of coupling to a number of PCI compatible master controllers, which are embedded within a peripheral component. The peripheral components may include, for example, a graphic adapter
16
a
, an expansion bus bridge
16
b
, a LAN adapter
16
c
and SCSI host bus adapter
16
d
. Each master controller within these peripheral components is capable of sending out a request (REQ) signal to the arbiter within the PCI bridge
12
via the PCI bus
14
requesting for data transfer through the PCI bus. On receiving the request (REQ), the PCI bridge
12
can issue a grant (GNT) signal to the master controller accepting its use of the PCI bus
14
.
Data transfer between different PCI compatible components (for example, a master controller and the north bridge of a computer chipset) can be realized through an interface control signal described below. In the beginning, a cycle frame (FRAME) is transmitted from an initiator (possibly a master controller or a north bridge) signaling the initiation of a data accessing period. The sending of a FRAME signal implies that a data transaction through the PCI bus has begun. As long as the FRAME signal remains at a low potential, it means the data transaction is still under way. Soon after the FRAME signal is out, valid address will be set up on address bus lines AD during the address phase. At the same time, valid bus commands (meeting PCI specifications) will be sent from the command/byte enable (CBE [
3
:
0
]) lines so that the target device will notice the kind of data transaction demanded by the initiator. In general, the command/byte enable uses four bits on four lines to encode 16 commands, and relevant details can be found in the PCI specifications. After valid address is out, the requested data will be put on the address/data bus AD in the so-called data phase. In the meantime, byte enable signals corresponding to the encoded bus command will be sent through the CBE lines for data transmission. When the FRAME signal is finally terminated by the initiator, this implies either the last set of data is out, or data transmission is complete. During the data transmission phase, the initiator ready (IRDY) signal and the target ready (TRDY) signal work with each other for indicating the state of affairs in the initiator and the target device. The two synchronize with each other so that data transmission can be carried out smoothly. During a data read operation, putting up an IRDY signal implies the initiator is ready to receive data. During a data write operation, putting up a TRDY signal implies the target is ready to receive data. In addition, there is a stop (STOP) signal that can be set up by the target device requesting the initiator to cancel the current data transaction.
FIG. 2
is a timing diagram showing the sequence of events at a PCI bus interface during a read operation. A period within which the entire process of data transfer is carried out using a PCI bus is known as a bus transaction period
20
. The bus transaction period
20
can be divided into an address phase
22
and several data phases such as
24
a
,
24
b
and
24
c
. Each data phase
24
a/b/c
can be further divided into a wait cycle
26
a/b/c
and a data transfer cycle
28
a/b/c
. Next, the operation of the PCI system is explained with respect to the various aforementioned controlling signals according to PCI specifications.
First, in cycle T
1
, the initiator will submit a FRAME signal indicating the start of a data transfer operation, and then a start address is submitted via the address/data bus AD for pin-pointing at a target device. At the same time, the CBE line will issue a read instruction. Thereafter, the CBE line will issue a byte enable signal. The byte enable signal is maintained throughout the entire data phase (including
24
a
,
24
b
and
24
c
). In cycle T
2
, the initiator will forward an initiator ready IRDY signal indicating data transfer can begin. If, at this moment, the target device is not ready yet, the initiator must wait until the target device is ready. The waiting period is known as a wait cycle
26
a
. Later, in cycle T
3
, the target device is ready and hence a target ready TRDY signal is issued by the target device. Therefore, during data transfer cycle
28
a
, data is read from the target device to the initiator. In cycle T
4
, the target ready TRDY signal is terminated signaling the end of data transfer. Next, the second set of data is being prepared while the wait cycle
26
b
of the second data transfer cycle
24
b
begins. In cycle T
5
, target ready TRDY signal is again issued implying that the second set of data is ready. When the initiator ready IRDY signal and the target ready TRDY signal are up during data transfer cycle
28
b
, the second set of data is transferred from the target device to the initiator. When the initiator could not read the incoming data fast enough, the initiator will terminate the initiator ready IRDY signal in cycle T
6
, for example. Since the target ready TRDY signal is still up, the wait cycle
26
c
is actually initiated by the initiator. As soon as the initiator is ready again, an initiator ready IRDY signal is submitted in cycle T
7
. Now, the initiator ready IRDY signal and the target ready TRDY signal are up again during data transfer cycle
28
c
, so the remaining third set of data are read from the target device to the initiator. Hence, the entire read operation is complete.
In the PCI specifications (for example, in version 2.2), a special type of data transfer mode commonly referred to as delayed transaction exists. The so-called delayed transaction is an operating sequence that is employed when the complete transfer of data could not be finished within the initial data phase. There are two main types of components that possibly require delayed transaction, namely, an input/output (I/O) controller and a bridging device. Usually, an I/O controller can process only one delay transaction at a time, whereas a bridging device can process a multiple of delayed transactions simultaneously thereby giving an improved system efficiency.
Conventional delayed transaction involves three cycles. First, the master controller will submit a request for using the PCI bus. Next, the target device will try to complete the operations requested by the master controller. Finally, the transaction is completed by the master controller. During the entire delayed transaction cycle, the master controller not only will continuously submit request signals, but will also seek out the current status of the target device through operations similar to polling. Thus, the PCI bus is fully occupied and hence unable to perform any other operations.
For a PCI system under the conventional delayed transaction mode, if a transaction needs to be re-tried, the master controller has to forward a request REQ signal to the PCI bus repeatedly. The master controller has to repeat the request REQ signal to the PCI bus until data are ready for transmission. Since the PCI bus is fully occupied when the master controller keeps putting up data requests, any other data transfer operations are impossible. Consequently, the PCI bus is very much underutilized.
In light of the foregoing, there is an urgent need to improve the degree of utilization of the PC

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