Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-08-26
2001-08-07
Etienne, Ario (Department: 2155)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S120000, C710S008000
Reexamination Certificate
active
06272582
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a PCI-PCI bridge between a primary PCI bus and a secondary PCI bus. More specifically, the present invention relates to a PCI-PCI bridge supported by an existing BIOS and allowing controlling of a plurality of PCI agents including a VGA device through the primary PCI.
2. Description of the Background Art
A PCI (Peripheral Component Interconnect) bus comes to be generally adopted especially for personal computers. PCI is a bus standard advocated by Intel Corporation, of which specification is determined and published by PCI Special Interest Group (PCI SIG) of the United States.
According to PCI bus standard, a device participating in PCI data transfer is referred to as an “agent.” According to PCI standard, agents are controlled by BIOS executed by a CPU, by a device driver and so on. PCI bus standard provides automatic configuration capability of automatically sensing a device connected to the bus at the time of power on and preparing system environment such as memory mapping for each system.
Recently, as personal computers come to have ever improved performance, it comes to be a common practice to execute, by a personal computer, image processing programs and the like which have conventionally been executed by a workstation. For this purpose, an LSI (semiconductor integrated circuit) for performing such a specific processing is often connected to a host CPU through a PCI bus in the personal computer. Implementation of a plurality of PCI devices in the integrated circuit is desirable in some cases. At that time, it is necessary to interface the PCI bus of the host with a PCI bus of an added device. Here, the PCI bus in the host CPU is referred to as a primary PCI bus, and the PCI bus of a circuit (add-in board) connected to the primary PCI bus is referred to as a secondary PCI bus.
If a secondary PCI bus is connected to the primary PCI bus and a plurality of PCI agents are connected to the secondary PCI bus, it is necessary for the host to control each PCI independent from each other. For this purpose, PCI standard employs data referred to as PCI configuration header. The header includes two types, that is, type “00” and type “01”. Type “00” header is recognized by the host CPU as one PCI agent, and type “01” header is prepared for the PCI-PCI bridge.
The PCI-PCI bridge of type “01”, however, suffers from various problems. For example, it can support limited BIOS only, it is difficult to support DMA (Direct Memory Access) function, and it is difficult to incorporate LSI core in a device having the secondary PCI bus. Accordingly, use of type “01” header is rather disadvantageous when various circuits for image processing are incorporated in one semiconductor integrated circuit device, one of which is a PCI agent. Data transfer through the primary and secondary PCI buses need be stable and at high speed. Here, generally, the secondary bus is faster than the primary bus. Accordingly, an FIFO (First In First Out memory) is used for the data transfer. If there should be a specification change, however, FIFO design must also be changed, resulting in longer time period necessary for the overall design.
Further, it is advantageous to ensure compatibility with an existing VGA device so that any trouble or accident at the time of boot-up may be displayed on the VGA device. Though it is possible to display an error message at the time of boot-up using the add-in board for the graphic processing mentioned above, such processing is complicated as compared with the process using the existing VGA device. Therefore, it is preferable that components including the VGA device are connected to the secondary PCI bus and that the components are switched as needed. Such approach, however, has been difficult for the PCI-PCI bridge of type “01” header.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a PCI-PCI bridge connecting a semiconductor integrated circuit device having a secondary PCI bus to a primary PCI bus without using type “01” header, and capable of independently controlling individual PCI agent.
Another object of the present invention is to provide a PCI-PCI bridge capable of connecting a secondary PCI bus and a primary PCI bus, where a VGA device as well as PCI agents are incorporated.
An additional object of the present invention is to provide a PCI-PCI bridge allowing, in a simple manner, error message display at the time of boot-up using an existing VGA device.
A still further object of the present invention is to provide a PCI-PCI bridge allowing DMA transfer.
A still further object of the present invention is to provide a PCI-PCI bridge capable of high speed data transfer between a main memory and a PCI agent or an operation circuit for performing a specific operation on the secondary PCI bus.
A still further object of the present invention is to provide an FIFO used for the PCI bridge and facilitating design of the PCI-PCI bridge.
The PCI-PCI bridge in accordance with the present invention is connected to a primary PCI bus and a secondary PCI bus, and includes a bridging circuit for connecting the secondary and primary PCI buses and for controlling data transfer therebetween. The bridging circuit has type “00” configuration header, and includes a circuit for identifying, at the time of configuration, one of a plurality of PCI agents on the secondary PCI bus based on a value of a function number field of a configuration command applied from a device driver, and for letting the identified agent execute configuration.
The PCI-PCI bridge employing type “00”, header is surely supported by BIOS. Though the bridge is not recognized by the BIOS as a PCI-PCI bridge, the bridge is capable of identifying one of a plurality of PCI agents on the secondary PCI bus using the function number field of the configuration header so as to allow the identified agent to perform configuration. As a result, it becomes possible for a device driver to flexibly control agents on the secondary PCI bus.
Preferably, the plurality of PCI agents include a VGA device and other PCI agents. The bridging circuit is operable selectively in one of a first mode in which a memory map for the VGA device only is active and a second mode in which PCI agents other than VGA are active.
That the switching is possible between the first mode in which only the VGA device is operable and the second mode in which PCI agents other than the VGA are operable enables simultaneous execution of a program using the VGA and operating in the conventional DOS, and a novel procedure by a PCI agent.
More preferably, the bridging circuit is boot-up in the first mode, and switched to the second mode by a device driver operating on a processor connected to the primary PCI bus.
Since the bridging circuit is activated in the first mode in which only the memory map for the VGA is active, display of an error message, for example, can readily be given by the VGA. Once the device driver starts its operation, the operation mode is switched to the second mode, and therefore execution of a processing using the PCI device can be started smooth.
More preferably, the PCI-PCI bridge further includes an operation circuit for performing a specific processing and capable of data transfer with the primary and secondary PCI buses. The bridging circuit manages data transmission/reception between the operation circuit and the primary and secondary buses.
Implementation of the operation circuit on the PCI-PCI bridge ensures powerful service for the host CPU. Especially when the amount of calculation is formidable as in a graphic processing, provision of a dedicated operation circuit reduces load on the host CPU.
More preferably, the PCI-PCI bridge further includes an on the fly direct data transfer circuit responsive to a trigger of direct data transfer from the main memory by the device driver for performing following designated data transfer without any intervention of the device driver, and responsive to a link list appended at a tail of a da
Kawai Hiroyuki
Streitenberger Robert
Etienne Ario
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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