Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1999-01-06
2000-08-15
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 1, 714 7, G06F 1100
Patent
active
061051462
ABSTRACT:
A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare. In addition to detecting errors and performing survival and maintenance operations, the SMC enhances system performance during normal operations by supporting master-target priority determinations to more efficiently arbitrate mastership of system busses such as the PCI bus.
REFERENCES:
patent: 5249187 (1993-09-01), Bruckert et al.
patent: 5533204 (1996-07-01), Tipley
patent: 5596729 (1997-01-01), Lester et al.
patent: 5864653 (1999-01-01), Tavallaci et al.
Gagliardi Louis R.
Miller Joseph Peter
Tavallaei Siamak
Beausoliel, Jr. Robert W.
Compaq Computer Corp.
Elisca Pierre E.
Harris Jonathan M.
Heim Michael F.
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