PCI device arbiter

Details PCI device arbiter PCI device arbiter

1999-07-21

2002-09-10

Wong, Peter (Department: 2781)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S110000, C710S113000

Reexamination Certificate

active

06449672

ABSTRACT:

BACKGROUND
The present invention relates to a method and apparatus for arbitrating between devices connected to an input/output bus, such as a peripheral component interconnect (PCI) bus.
Computer systems typically include one or more buses which interconnect a plurality of devices. For instance, the conventional system
100
shown in
FIG. 1
includes a central processing unit (CPU)
102
connected to a cache/memory system
110
via host bus
104
. The CPU
102
can include any conventional microprocessor, such as a Motorola PowerPC™ RISC microprocessor. This microprocessor uses a protocol in which memory accesses are divided into address and data tenures.
The host bus
104
is also connected to a conventional bus bridge
106
, which, in turn, is connected to an input/output bus, such as a peripheral component interconnect (PCI) bus
112
. Various types of devices can be connected to the PCI bus, including various video and graphics accelerator cards, audio cards, telephony cards, SCSI (Small Computer Systems Interface) adapters, network interface cards, etc. These units are generically represented by PCI devices
114
,
116
,
118
and
120
. In addition, although not shown, the PCI bus
112
can accommodate additional bus bridges which provide access to other buses, such as other PCI buses or ISA (Industry Standard Architecture) buses.
Although not shown, the PCI bus
112
includes a central arbiter connected thereto for arbitrating between plural requests by different PCI devices to access the PCI bus
112
. Each device typically has a unique pair of request and grant signal connections to the central arbiter. A device requests the bus by asserting its request signal. When the arbiter determines that the device may use the bus, it asserts the grant signal. The grant signal gives the respective PCI device permission to use the bus for one transaction. If the device requires additional access to the bus, it must reassert its request signal. The arbitration algorithm may comprise some form of priority or round-robin protocol, or some hybrid form of these techniques.
Conventional logic
200
for interfacing a PCI device to the PCI bus
112
is shown in FIG.
2
. The interface
200
includes two flip-flops
202
,
204
. Data is fed into flip-flop
204
via line
210
, while an enable signal is fed into flip-flop
202
via line
208
. The outputs of the flip-flops on lines
212
and
214
are fed to tristate buffer
206
, which outputs the data on line
216
. In operation, the enable signal “EN” determines whether the data stored within flip-flop
204
is fed out to the PCI bus
112
. The clock signals supplied to the flip-flops ensures that their output is properly synchronized with the PCI bus
112
.
Further details regarding the PCI standard can be found in PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group, Dec. 18, 1998, which is incorporated herein by reference in its entirety.
Although the PCI bus protocol is in widespread use today, it has a number of limitations. For instance, each device which is coupled to the bus requires a request and grant pin for interfacing with the PCI bus arbiter. For instance, three devices would require the use of six pins. PCI bus arbiters typically include a fixed number of ports. The PCI bus also has load limits. Under the published standard, the maximum load value is ten where a PCI device is one load and a connector presents two loads. Hence, the PCI bus may be only capable of supporting a finite number of devices coupled to the bus.
These problems can be addressed by providing an additional bus bridge. That is, a bus bridge can be coupled to the PCI bus, which provides access to an expansion bus. The expansion bus, in turn, can support additional peripheral devices. However, bus bridges impose added regimes of clock cycles, which may lead to processing delays. Also, the bus bridge introduces an additional hierarchical layer in the bus protocol, which may causes complications during testing of the peripheral devices. In other words, because the peripheral device is buried in multiple bus layers, it may be difficult to track the behavior of the peripheral device under test. Bus bridges also add to the cost of the system.
It is possible to group together multiple peripheral devices in a common chip ASIC to reduce the space occupied by the plural devices and to more efficiently utilize system resources. However, this design does not address the above-noted problems, since the ASIC still includes separate devices which continue to interact with the PCI bus
112
in the same manner as conventional discrete devices. For instance, each of the PCI devices retains its pair of request and grant connections to the bus
112
, resulting in the use of the same number of ports in the PCI bus arbiter as in the case of discrete devices.
SUMMARY
It is accordingly one exemplary objective of the present invention to provide a more efficient way of interfacing PCI devices to a PCI bus.
This objective is achieved according to the present invention by providing a PCI ASIC unit comprising multiple PCI agents (corresponding to discrete PCI devices) and an internal arbiter connected to a PCI bus. The agents transmit requests to use the PCI bus to the internal arbiter. On the basis of these requests, the internal arbiter generates a single request for output to an external PCI bus arbiter. The internal arbiter also selects which one of the agents shall be granted access to the bus. When a grant signal is received by the internal arbiter, the internal arbiter establishes a connection between the selected agent and the PCI bus such that the selected agent is granted access to the PCI bus to exchange data therewith. The selected agent corresponds to that agent which sent out its request to the external arbiter.
In the above-described configuration, the PCI ASIC has only a single request/grant pair which connects the ASIC to the PCI bus. This reduces the number of external PCI arbiter ports required to service the PCI ASIC. Further, the single request signal is sent out very quickly, such that the transaction is not unnecessarily delayed, in contrast to conventional bus bridge solutions.
According to another feature of the present invention, a single timing unit is used to control the timing of the interface to the multiple bus agents. Hence, all internal agents “look” the same at the interface. This reduces the complexity of the PCI ASIC and simplifies the testing of the multiple agents.
According to yet another feature of the present invention, a previously selected request is routed out for one clock after it finishes using the bus. The subsequent request sent out of the ASIC is the logical OR of individual requests. Once an individual request is selected, it is the only one which is sent. The delay of the logical OR is a useful measure to ensure that a previously selected agent can perform a PCI retry operation without interference from other agents.


REFERENCES:
patent: 5592631 (1997-01-01), Kelly et al.
patent: 5774684 (1998-06-01), Haines et al.
patent: 5870570 (1999-02-01), Chambers et al.
patent: 6308248 (2001-10-01), Welker et al.
“PowerPC 601, RISC Microprocessor User's Manual,” Motorola Inc., 1993, pp. 6-16 to 6-17 and 9-1 to 9-12.

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